Patents by Inventor Harry W. Scrivener, III

Harry W. Scrivener, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multiprocessor computing apparatus with optional coherency directory
    Patent number: 6012127
    Abstract: A multiprocessor computing apparatus including a plurality of processors each having a cache memory and preferably arranged in nodes on a system bus. A first cache coherency providing mechanism coupled to the processors for achieving system level cache coherency. A second cache coherency providing mechanism is also provided. When an error is detected in the first cache coherency providing mechanism, this mechanism is disabled and cache coherency is achieved by the second cache coherency providing mechanism. In a preferred embodiment, the first mechanism includes coherency directories and the second mechanism includes bus snooping.
    Type: Grant
    Filed: December 12, 1997
    Date of Patent: January 4, 2000
    Assignee: Intel Corporation
    Inventors: Edward A. McDonald, James M. Ottinger, Harry W. Scrivener, III