Patents by Inventor Harsanjeet Singh
Harsanjeet Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9785542Abstract: A method for debugging test procedures for automated device testing is disclosed. The method comprises receiving a command to update at least one modified test procedure modified during a first debugging session and saving state information for a test plan, wherein the state information comprises information regarding a breakpoint entry location, and wherein the modified test procedure is invoked within the test plan. The method subsequently comprises suspending execution of the test plan and unloading the modified test procedure. It also comprises compiling the modified test procedure to produce a compiled file and then reloading the test procedure into the test plan using the compiled file. Finally, it comprises resuming execution of the modified test procedure in a second debugging session and breaking the execution during the second debugging session at a breakpoint corresponding to the breakpoint entry location.Type: GrantFiled: April 16, 2013Date of Patent: October 10, 2017Assignee: ADVANTEST CORPORATIONInventors: Mark Elston, Leon Chen, Harsanjeet Singh, Hironori Maeda, Ankan Pramanick, Youbi Katsu
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Patent number: 9274911Abstract: A method for using shared pins in a concurrent test execution environment is disclosed. The method relates to scheduling tests in concurrently executing test flows for automated test equipment (ATE) in a way so that resources can be shared between the test flows. The method comprises determining if any of a plurality of splits used by a first test contains at least one resource that is shared, wherein the first test and a second test are sequenced for execution in two separate concurrently executing test flows. The method further comprises determining if the first test should execute before the second test if the split is associated with resources required by both the second and first tests. Finally the method comprises reserving the split containing the at least one shared resource for access by the first test before beginning execution of the first test.Type: GrantFiled: February 21, 2013Date of Patent: March 1, 2016Assignee: ADVANTEST CORPORATIONInventors: Mark Elston, Harsanjeet Singh, Ankan Pramanick, Leon Lee Chen, Hironori Maeda, Chandra Pinjala, Ramachandran Krishnaswamy
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Publication number: 20140310693Abstract: A method for debugging test procedures for automated device testing is disclosed. The method comprises receiving a command to update at least one modified test procedure modified during a first debugging session and saving state information for a test plan, wherein the state information comprises information regarding a breakpoint entry location, and wherein the modified test procedure is invoked within the test plan. The method subsequently comprises suspending execution of the test plan and unloading the modified test procedure. It also comprises compiling the modified test procedure to produce a compiled file and then reloading the test procedure into the test plan using the compiled file. Finally, it comprises resuming execution of the modified test procedure in a second debugging session and breaking the execution during the second debugging session at a breakpoint corresponding to the breakpoint entry location.Type: ApplicationFiled: April 16, 2013Publication date: October 16, 2014Applicant: Advantest CorporationInventors: Mark ELSTON, Leon CHEN, Harsanjeet SINGH, Hironori MAEDA, Ankan PRAMANICK, Youbi KATSU
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Publication number: 20140237291Abstract: A method for using shared pins in a concurrent test execution environment is disclosed. The method relates to scheduling tests in concurrently executing test flows for automated test equipment (ATE) in a way so that resources can be shared between the test flows. The method comprises determining if any of a plurality of splits used by a first test contains at least one resource that is shared, wherein the first test and a second test are sequenced for execution in two separate concurrently executing test flows. The method further comprises determining if the first test should execute before the second test if the split is associated with resources required by both the second and first tests. Finally the method comprises reserving the split containing the at least one shared resource for access by the first test before beginning execution of the first test.Type: ApplicationFiled: February 21, 2013Publication date: August 21, 2014Applicant: ADVANTEST CORPORATIONInventors: Mark Elston, Harsanjeet Singh, Ankan Pramanick, Leon Lee Chen, Hironori Maeda, Chandra Pinjala, Ramachandran Krishnaswamy
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Patent number: 8255198Abstract: Test program development for a semiconductor test system, such as automated test equipment (ATE), using object-oriented constructs is described. The invention provides a method for describing test system resources, test system configuration, module configuration, test sequence, test plan, test condition, test pattern, and timing information in general-purpose object-oriented constructs, e.g., C++ objects and classes. In particular, the modularity of program development is suitable for developing test programs for an open architecture semiconductor test system.Type: GrantFiled: March 26, 2010Date of Patent: August 28, 2012Assignee: Advantest CorporationInventors: Ramachandran Krishnaswamy, Harsanjeet Singh, Ankan Pramanick, Mark Elston, Leon Chen, Toshiaki Adachi, Yoshihumi Tahara
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Publication number: 20100192135Abstract: Test program development for a semiconductor test system, such as automated test equipment (ATE), using object-oriented constructs is described. The invention provides a method for describing test system resources, test system configuration, module configuration, test sequence, test plan, test condition, test pattern, and timing information in general-purpose object-oriented constructs, e.g., C++ objects and classes. In particular, the modularity of program development is suitable for developing test programs for an open architecture semiconductor test system.Type: ApplicationFiled: March 26, 2010Publication date: July 29, 2010Applicant: Advantest CorporationInventors: Ramachandran KRISHNASWAMY, Harsanjeet SINGH, Ankan PRAMANICK, Mark ELSTON, Leon CHEN, Toshiaki ADACHI, Yoshihumi TAHARA
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Publication number: 20080016396Abstract: There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test module emulation sections for emulating the plurality of test modules generating the test signal based on different cycles, a control emulation section for emulating a control apparatus for controlling the test of the devices under test, a synchronous emulation section for generating test signal generating timings, at which each of the plurality of test module emulation sections is to generate the test signal in simulation corresponding to cycle time of the test module emulation section, based on instructions from the control emulation section, a timing alignment section for aligning the plurality of test signal generating timings generated by the synchronous emulation section in order of time, and outputting them one by one, and a schedule section for causing the test module emulation section corresponding to one ofType: ApplicationFiled: September 24, 2007Publication date: January 17, 2008Applicant: ADVANTEST CORPORATIONInventors: Shinsaku Higashi, Seiji Ichiyoshi, Ankan Pramanick, Mark Elston, Leon Chen, Robert Sauer, Ramachandran Krishnaswamy, Harsanjeet Singh, Toshiaki Adachi, Yoshihumi Tahara
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Publication number: 20080010524Abstract: There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test module emulation sections for emulating the plurality of test modules generating the test signal based on different cycles, a control emulation section for emulating a control apparatus for controlling the test of the devices under test, a synchronous emulation section for generating test signal generating timings, at which each of the plurality of test module emulation sections is to generate the test signal in simulation corresponding to cycle time of the test module emulation section, based on instructions from the control emulation section, a timing alignment section for aligning the plurality of test signal generating timings generated by the synchronous emulation section in order of time, and outputting them one by one, and a schedule section for causing the test module emulation section corresponding to one ofType: ApplicationFiled: September 24, 2007Publication date: January 10, 2008Applicant: ADVANTEST CORPORATIONInventors: Shinsaku Higashi, Seiji Ichiyoshi, Ankan Pramanick, Mark Elston, Leon Chen, Robert Sauer, Ramachandran Krishnaswamy, Harsanjeet Singh, Toshiaki Adachi, Yoshihumi Tahara
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Patent number: 7209851Abstract: A method for managing a pattern object file in a modular test system is disclosed. The method includes providing a modular test system, where the modular test system comprises a system controller for controlling at least one site controller, and where the at least one site controller controls at least one test module and its corresponding device under test (DUT). The method further includes creating an object file management framework for establishing a standard interface between vendor-supplied pattern compilers and the modular test system, receiving a pattern source file, creating a pattern object metafile based on the pattern source file using the object file management framework, and testing the device under test through the test module using the pattern object metafile.Type: GrantFiled: August 13, 2004Date of Patent: April 24, 2007Assignee: Advantest America R&D Center, Inc.Inventors: Harsanjeet Singh, Ankan Pramanick, Mark Elston, Yoshifumi Tahara, Toshiaki Adachi
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Publication number: 20050154550Abstract: A method for managing a pattern object file in a modular test system is disclosed. The method includes providing a modular test system, where the modular test system comprises a system controller for controlling at least one site controller, and where the at least one site controller controls at least one test module and its corresponding device under test (DUT). The method further includes creating an object file management framework for establishing a standard interface between vendor-supplied pattern compilers and the modular test system, receiving a pattern source file, creating a pattern object metafile based on the pattern source file using the object file management framework, and testing the device under test through the test module using the pattern object metafile.Type: ApplicationFiled: August 13, 2004Publication date: July 14, 2005Applicant: Advantest America R&D Center, Inc.Inventors: Harsanjeet Singh, Ankan Pramanick, Mark Elston, Yoshifumi Tahara, Toshiaki Adachi
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Publication number: 20050039079Abstract: There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test module emulation sections for emulating the plurality of test modules generating the test signal based on different cycles, a control emulation section for emulating a control apparatus for controlling the test of the devices under test, a synchronous emulation section for generating test signal generating timings, at which each of the plurality of test module emulation sections is to generate the test signal in simulation corresponding to cycle time of the test module emulation section, based on instructions from the control emulation section, a timing alignment section for aligning the plurality of test signal generating timings generated by the synchronous emulation section in order of time, and outputting them one by one, and a schedule section for causing the test module emulation section corresponding to one ofType: ApplicationFiled: March 31, 2004Publication date: February 17, 2005Inventors: Shinsaku Higashi, Seiji Ichiyoshi, Ankan Pramanick, Mark Elston, Leon Chen, Robert Sauer, Ramachandran Krishnaswamy, Harsanjeet Singh, Toshiaki Adachi, Yoshihumi Tahara
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Publication number: 20040225459Abstract: Test program development for a semiconductor test system, such as automated test equipment (ATE), using object-oriented constructs is described. The invention provides a method for describing test system resources, test system configuration, module configuration, test sequence, test plan, test condition, test pattern, and timing information in general-purpose object-oriented constructs, e.g., C++ objects and classes. In particular, the modularity of program development is suitable for developing test programs for an open architecture semiconductor test system.Type: ApplicationFiled: February 6, 2004Publication date: November 11, 2004Applicant: Advantest CorporationInventors: Ramachandran Krishnaswamy, Harsanjeet Singh, Ankan Pramanick, Mark Elston, Leon Chen, Toshiaki Adachi, Yoshihumi Tahara