Patents by Inventor Harsaran Singh Bhatia

Harsaran Singh Bhatia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6203926
    Abstract: A corrosion resistant, multi-layer structure on a substrate including an adhesion metallic layer on the substrate, a cushion metallic layer on the adhesion layer, a diffusion barrier layer on the cushion layer, and an impermeable gold layer that encapsulates all the layers, is substantially even on all sides of the layers, and contacts a region on the substrate adjacent the layers to prevent oxidation and corrosion.
    Type: Grant
    Filed: December 28, 1999
    Date of Patent: March 20, 2001
    Assignee: International Business Machines Corporation
    Inventors: Umar Moez Uddin Ahmad, Harsaran Singh Bhatia, Satya Pal Singh Bhatia, Hormazdyar Minocher Dalal, William Henry Price, Sampath Purushothaman
  • Patent number: 3987216
    Abstract: A method is disclosed for forming Schottky barrier junctions having improved barrier height characteristics. The method involves the use of a layer of polysilicon deposited upon the Schottky metal prior to sintering. The polysilicon layer acts as a source from which silicon is diffused into the metal during the sintering operation. After sintering the junction is quenched or cooled at a rapid rate whereby outdiffusion of the silicon is prevented.
    Type: Grant
    Filed: December 31, 1975
    Date of Patent: October 19, 1976
    Assignee: International Business Machines Corporation
    Inventors: Harsaran Singh Bhatia, Harry Charles Calhoun, Robert Leonard Melhado, Randolph Huff Schnitzel
  • Patent number: 3955210
    Abstract: A complementary field effect transistor structure which eliminates the problems caused by parasitic currents between devices. The currents are contained within parasitic bipolar devices formed between the various regions of the FETs. A portion of the collector current of the parasitic bipolar devices is drained away so that the loop gain is less than one. This is achieved by placing guard regions of conductivity type which are the same as the channel type of the transistors adjacent said regions. The guard region is preferably in the form of a continuous ring around its associated FET.
    Type: Grant
    Filed: December 30, 1974
    Date of Patent: May 4, 1976
    Assignee: International Business Machines Corporation
    Inventors: Harsaran Singh Bhatia, Gerald Dennis O'Rourke, Siegfried K. Wiedmann