Abstract: A controller includes: a processor; and interface circuitry for multiple interfaces. The interface circuitry is coupled to the processor and is configured to: receive load sequences from the processor, the load sequences including a respective load sequence for each of the multiple interfaces, each load sequence including image data intervals and idle intervals; determine a duration for each of the idle intervals; and separately control a sleep mode for each of the multiple interfaces responsive to each of the idle intervals.

Abstract: A circuit including a device including a receiver having a receiver input, a receiver output, and a bias current input and a bias generator having a bias current output coupled to the bias current input. The device also includes a buffer having a buffer input, an enable input, and a buffer output, the buffer input coupled to the receiver output and a delay circuit having a delay output coupled to the enable input.