Patents by Inventor Harsh D. Sharma
Harsh D. Sharma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7131034Abstract: A signal duration measurement system compares a known duration, T1, of a test data signal with the duration, T2, of a state of a signal under test. In one embodiment, if T2 compares favorably with T1, then the circuit generating the signal under test ‘passes.’ Otherwise the signal under test ‘fails,’ and a problem has been identified. Furthermore, in one embodiment, T1 can be selectively adjusted to more accurately measure T2. In one embodiment, the test data signal is allowed to travel a signal path, having a known signal propagation delay time, during a single state of the signal under test. The data signal at the beginning of the state, e.g. during the rise of the signal under test, is compared to the data signal captured at the end of the state, e.g. during the fall of the signal under test. If the initial and captured data signals are the same, then the duration of the state of the signal under test is greater than or equal to the signal propagation delay time.Type: GrantFiled: November 12, 2002Date of Patent: October 31, 2006Assignee: Sun Microsystems, Inc.Inventors: Nadeem N. Eleyan, Harsh D. Sharma, Howard L. Levy, Hong S. Kim
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Patent number: 7116126Abstract: A method of transmitting adjacent signals is disclosed. Sensing is performed on signals in the group and adjacent signals are either switched or delayed if the adjacent signals are switching at the same time. The method is used in networks where coupling and capacitance effects are possible.Type: GrantFiled: October 16, 2001Date of Patent: October 3, 2006Assignee: Sun Microsystems, Inc.Inventors: Nayon Tomsio, Harsh D. Sharma
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Patent number: 7036098Abstract: Signal state durations, such as the pulse-width, of on-chip signals are often critical to the successful operation of an integrated circuit. The signal state durations measured by on-chip technology provide signal state duration information to an on-chip signal state duration control system. The signal state duration control system uses the information to adjust the signal state duration of an on-chip signal. In one embodiment, the signal state duration of the on-chip signal is the pulse width of the on-chip signal. The signal duration measurement and adjustment system is, for example, useful for measuring the state duration of signals such as self-resetting signals, which are difficult to externally measure and adjust signal state durations using on-chip technology.Type: GrantFiled: June 30, 2003Date of Patent: April 25, 2006Assignee: Sun Microsystems, Inc.Inventors: Nadeem N. Eleyan, Harsh D. Sharma, Howard L. Levy, Hong S. Kim
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Patent number: 7016422Abstract: A method of transmitting and prioritizing signals is disclosed. Higher priority signals are switched while lower priority signals are delayed until the higher priority signals have completed switching. The method is used in networks where coupling and capacitance effects are possible.Type: GrantFiled: August 9, 2001Date of Patent: March 21, 2006Assignee: Sun Microsystems, Inc.Inventors: Harsh D. Sharma, Nayon Tomsio
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Patent number: 6891403Abstract: The locked frequency of a PLL is used to latch a test signal through various latching devices (flip-flops or the like). Various different delays are selectively applied to the test signal to provide a delayed test signal and the delayed test signal is measured to determine whether the delay in the test signal matches the jitter in the locked frequency of the PLL. When the delay in the test signal matches the jitter in the locked frequency of the PLL, the respective delay of the test-signal is used to determine the effective locked frequency of the PLL.Type: GrantFiled: October 22, 2002Date of Patent: May 10, 2005Assignee: Sun Microsystems, Inc.Inventors: Harsh D. Sharma, Howard L. Levy, Hong Kim, Nadeem N. Eleyan
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Publication number: 20040268280Abstract: Signal state durations, such as the pulse-width, of on-chip signals are often critical to the successful operation of an integrated circuit. Commonly assigned patent application Ser. No. 10/292329 entitled “On-Chip Measurement of Signal State Duration”, describes examples of a signal state duration measurement system technology that measures signal state durations using on-chip technology. The signal state durations measured by on-chip technology provide signal state duration information to an on-chip signal state duration control system. The signal state duration control system uses the information to adjust the signal state duration of an on-chip signal. In one embodiment, the signal state duration of the on-chip signal is the pulse width of the on-chip signal.Type: ApplicationFiled: June 30, 2003Publication date: December 30, 2004Inventors: Nadeem N. Eleyan, Harsh D. Sharma, Howard L. Levy, Hong S. Kim
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Patent number: 6737902Abstract: Provided are a method and a system to distribute clock signals in digital circuits to ensure that the multiple clock signals reach multiple loads associated with the digital circuit, concurrently. To that end, an off-chip set of clock paths, which includes one or more clock buffers, are connected between two sets of clock paths on an integrated digital circuit. The multiple clock signals are routed to the off-chip set of clock paths to reduce, or remove, propagational delay in multiple clock signals that arise from the propagation of the same through the on-chip clock paths. This is achieved by the clock paths of the off-chip set of clock paths having differing resistivities, differing lengths or both.Type: GrantFiled: May 16, 2002Date of Patent: May 18, 2004Assignee: Sun Microsystems, Inc.Inventors: Nayon Tomsio, Avi Liebermensch, Harsh D Sharma
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Publication number: 20040093535Abstract: A signal duration measurement system compares a known duration, T1, of a test data signal with the duration, T2, of a state of a signal under test. In one embodiment, if T2 compares favorably with T1, then the circuit generating the signal under test ‘passes.’ Otherwise the signal under test ‘fails,’ and a problem has been identified. Furthermore, in one embodiment, T1 can be selectively adjusted to more accurately measure T2. In one embodiment, the test data signal is allowed to travel a signal path, having a known signal propagation delay time, during a single state of the signal under test. The data signal at the beginning of the state, e.g. during the rise of the signal under test, is compared to the data signal captured at the end of the state, e.g. during the fall of the signal under test. If the initial and captured data signals are the same, then the duration of the state of the signal under test is greater than or equal to the signal propagation delay time.Type: ApplicationFiled: November 12, 2002Publication date: May 13, 2004Inventors: Nadeem N. Eleyan, Harsh D. Sharma, Howard L. Levy, Hong S. Kim
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Publication number: 20040075477Abstract: In some embodiments, the present application describes an on-chip system and method of determining the effective locked frequency of a PLL. The locked frequency of the PLL is used to latch a test signal through various latching devices (flip-flops or the like). Various different delays are selectively applied to the test signal to provide a delayed test signal and the delayed test signal is measured to determined whether the delay in the test signal matches the jitter in the locked frequency of the PLL. When the delay in the test signal match the jitter in the locked frequency of the PLL, the respective delay of the test signal is used to determine the effective locked frequency of the PLL.Type: ApplicationFiled: October 22, 2002Publication date: April 22, 2004Applicant: Sun Microsystems, Inc.Inventors: Harsh D. Sharma, Howard L. Levy, Hong Kim, Nadeem N. Eleyan
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Publication number: 20030214340Abstract: Provided are a method and a system to distribute clock signals in digital circuits to ensure that the multiple clock signals reach multiple loads associated with the digital circuit, concurrently. To that end, an off-chip set of clock paths, which includes one or more clock buffers, are connected between two sets of clock paths on an integrated digital circuit. The multiple clock signals are routed to the off-chip set of clock paths to reduce, or remove, propagational delay in multiple clock signals that arise from the propagation of the same through the on-chip clock paths. This is achieved by the clock paths of the off-chip set of clock paths having differing resistivities, differing lengths or both.Type: ApplicationFiled: May 16, 2002Publication date: November 20, 2003Applicant: SUN MICROSYSTEMS, INC.Inventors: Nayon Tomsio, Avi N. Liebermensch, Harsh D. Sharma
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Publication number: 20030120982Abstract: The present invention describes a method and an apparatus for zero skew signal transition detection between multiple communication paths. The signal transition at the transition point is detected by sampling the signal before the transition point. A transition detection pulse is generated when the signal begins to transition at the transition point. The transition detection pulse can be used to adjust the signal transition on multiple adjacent parallel paths with zero skew to obtain desired coupling between the paths. The width of transition detection pulse can be adjusted to match the transition period of the signal.Type: ApplicationFiled: December 21, 2001Publication date: June 26, 2003Inventors: Howard L. Levy, Harsh D. Sharma, Nayon Tomsio
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Publication number: 20030072332Abstract: A method of transmitting adjacent signals is disclosed. Sensing is performed on signals in the group and adjacent signals are either switched or delayed if the adjacent signals are switching at the same time. The method is used in networks where coupling and capacitance effects are possible.Type: ApplicationFiled: October 16, 2001Publication date: April 17, 2003Inventors: Nayon Tomsio, Harsh D. Sharma
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Publication number: 20030031194Abstract: A method of transmitting and prioritizing signals is disclosed. Higher priority signals are switched while lower priority signals are delayed until the higher priority signals have completed switching. The method is used in networks where coupling and capacitance effects are possible.Type: ApplicationFiled: August 9, 2001Publication date: February 13, 2003Inventors: Harsh D. Sharma, Nayon Tomsio