Patents by Inventor Harsh Dev
Harsh Dev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7886238Abstract: Systems and methods to optimize a layout based on the yield analysis is disclosed. The method includes generating an integrated circuit layout having two or more layers of wire interconnect to form net segments and having one or more via contact layers to couple net segments in the wire interconnect together. The method further includes performing a yield analysis of the net segments in the integrated circuit layout and displaying the net segments with a visual depiction of the yield analysis using multiple levels of opacity to reflect yield scores of the net segments in the integrated circuit layout.Type: GrantFiled: November 28, 2006Date of Patent: February 8, 2011Assignee: Cadence Design Systems, Inc.Inventors: Harsh Dev Sharma, Rajeev Srivastava, Srinivas R. Kommoori, Bharat Bhushan, Mithunjoy Parui, Albert Lee
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Patent number: 7810063Abstract: According to various embodiments of the invention electronic circuit design information can be presented to a designer by determining an electronic circuit comprising at least two gates and by determining a distance of one gate relative to another gate in a stage. A visual indicator for the stage can be calculated based on the distances between at least two gates in the stage. The visual indicator can then be displayed. The visual indicator can be a color and the relative distance can be indicated by brightness, hue or saturation, etc. Alternatively, the visual indicator can be a pattern and the relative distance between at least two gates can be indicated by darkness of the pattern.Type: GrantFiled: February 1, 2007Date of Patent: October 5, 2010Assignee: Cadence Design Systems, Inc.Inventors: Harsh Dev Sharma, Po-chiang Albert Lee, Rajeev Srivastava, Srinivas R. Kommoori, Bharat Bhushan, Mithunjoy Parui
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Patent number: 7600208Abstract: Disclosed are methods, systems and apparatus for automatically placing decoupling capacitors in an integrated circuit to compensate for voltage drops that might otherwise occur in a power grid. In one embodiment of the invention, the method includes generating one or more regions of the integrated circuit design, with each region having one or more cells, determining an amount of decoupling capacitance required in each region of the integrated circuit design by analyzing each cell in the region, and adding sufficient decoupling capacitor cells to the region to compensate for the potential voltage drop.Type: GrantFiled: January 31, 2007Date of Patent: October 6, 2009Assignee: Cadence Design Systems, Inc.Inventors: Harsh Dev Sharma, Rajeev Srivastava, Srivinas R. Kommoori, Bharat Bhushan, Mithunjoy Parui, Albert Lee
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Patent number: 6208907Abstract: A method and apparatus is provided for enabling the transformation of a domino circuit to a static circuit without requiring the re-design of the chip or integrated circuit mask set. The domino circuit masks may be designed to include additional unconnected devices as appropriate which may be added or connected into the circuit after chip design release by changing only interconnection masks. Spare devices can be added and selectively used to make a domino circuit metal-mask programmable into a logically equivalent static circuit. In a first exemplary method, extra devices are added to, and/or existing devices are re-wired in the domino circuitry to make a complementary equivalent static gate. In a second exemplary methodology, the domino circuit is converted into a pseudo-NMOS circuit using devices already available in the circuit and modifying the circuit connections thereto.Type: GrantFiled: January 30, 1998Date of Patent: March 27, 2001Assignee: International Business Machines CorporationInventors: Christopher McCall Durham, Visweswara Rao Kodali, Douglas Ele Martin, Harsh Dev Sharma
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Patent number: 6107852Abstract: A method and device are disclosed for the reduction of the penalty associated with inserting a latch in a circuit which is utilized to implement an integrated circuit in a data-processing system. A semiconductor device is disclosed which includes a main latch circuit, a feedback latch circuit and an output terminal. The main latch circuit is capable of receiving an input data signal and an input clock signal. The main latch circuit generates a latch output signal in response to the input data and clock signals. The feedback latch circuit is capable of receiving the latch output signal from the main latch circuit and storing the latch output signal. The feedback latch circuit is capable of generating a feedback latch circuit output signal which is received by the main latch circuit to maintain the latch output signal. The output terminal of the device is coupled to the feedback latch circuit for outputting a device output signal which is equal to the feedback latch circuit output signal.Type: GrantFiled: May 19, 1998Date of Patent: August 22, 2000Assignee: International Business Machines CorporationInventors: Christopher McCall Durham, Michael Ju Hyeok Lee, Visweswara Rao Kodali, Harsh Dev Sharma
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Patent number: 6037804Abstract: A reduced-power integrated circuit includes a circuit data input, a circuit data output, and at least one row of dynamic logic. The row of dynamic logic includes a row clock input, a row data input, and a row data output coupled to the circuit data output, where a value received at the row data input is derived from the value at the circuit data input. The integrated circuit further includes a comparator that compares current and previous values at the circuit data input and a switch that selectively sets the row clock signal received at the row clock input to an inactive state and temporarily maintains the row clock signal in the inactive state in response to the comparator detecting that the current previous values of at the circuit data input are equivalent. Consequently, the row of dynamic logic does not (and need not) reevaluate the circuit data input value, and power dissipation is reduced.Type: GrantFiled: March 27, 1998Date of Patent: March 14, 2000Assignee: International Business Machines CorporationInventors: Christopher McCall Durham, Visweswara Rao Kodali, Michael Ju Hyeok Lee, Douglas Ele Martin, Harsh Dev Sharma
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Patent number: 5664911Abstract: A method for removing a contaminant from a treatment region of a contaminated region of a site in the earth having water therein and being contaminated with the contaminant includes heating the earth by establishing an electric field through the treatment region. The electric field gives rise to an electric conduction or displacement current through the treatment region. The electric current electrically heats at least a portion of the treatment region to a temperature below the boiling point of water to evaporate the water. A vacuum is drawn in a nether region of the site to collect water vapor evolved from the water and contaminant vapor evolved from the contaminant by movement of air from the surface of the earth, while the water vapor strips the contaminant from the earth. The contaminant vapor is disposed of in an innocuous manner.Type: GrantFiled: July 23, 1996Date of Patent: September 9, 1997Assignee: IIT Research InstituteInventors: Jack E. Bridges, Guggilam C. Sresty, Harsh Dev
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Patent number: 5586213Abstract: Ionic contact is established and maintained between electrodes and soil in ohmic heating of a subsurface formation for recovery of volatile and semi-volatile materials, such as hazardous waste, hydrocarbon-like materials, and valuable minerals having thermally responsive properties. A compressed, dry sponge is wrapped around an electrode, which is then inserted into a bore hole. A conductive liquid is added to the bore hole, causing the sponge to swell, creating a stable and substantial interface for the flow of heating currents.Type: GrantFiled: February 5, 1992Date of Patent: December 17, 1996Assignee: IIT Research InstituteInventors: Jack E. Bridges, Guggilam C. Sresty, Harsh Dev, Richard Jambor
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Patent number: 4670634Abstract: A water-containing region at or near the surface of the earth, such as a landfill, that is contaminated with hazardous materials is decontaminated by heating the region with bound radio frequency energy from a bound-wave transmission line excitor array disposed outside the region to a temperature to boil water and thereby increase the permeability of the region. The heating is continued by dielectric heating after water has boiled from at least a portion of the region to heat the portion to elevated temperatures substantially above the boiling point of water. The materials may then be rendered innocuous in situ in a number of ways, as by pyrolysis, thermally assisted decomposition, or reaction with an introduced reagent, such as oxygen. The materials may also be driven from the region, as by distillation or by evaporation and steam drive and then collected and disposed of, as by incineration.Type: GrantFiled: April 5, 1985Date of Patent: June 2, 1987Assignee: IIT Research InstituteInventors: Jack E. Bridges, Harsh Dev, Richard H. Snow, Allen Taflove
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Patent number: 4485868Abstract: A method of electromagnetic heating in situ recovers liquid hydrocarbons from an earth formation containing viscous hydrocarbonaceous liquid and water in an inorganic matrix where the formation is substantially impermeable to fluids under native conditions. A block of the earth formation is substantially uniformly heated with electromagnetic power to a temperature at which the viscous hydrocarbonaceous liquid is relatively fluid and a portion of the water vaporizes to water vapor at a pressure sufficient to overcome the capillary pressure of the liquid in the matrix. Water vapor thereupon escaping from the block under such pressure is recovered with hydrocarbonaceous liquid driven thereby. The magnitude of the electromagnetic power is controlled to limit the current recovery ratio of water vapor to hydrocarbonaceous liquid below a predetermined limit assuring substantial recovery of the hydrocarbonaceous liquid prior to the driving off of substantially all the water.Type: GrantFiled: September 29, 1982Date of Patent: December 4, 1984Assignee: IIT Research InstituteInventors: Guggilam C. Sresty, Harsh Dev, Richard H. Snow, Jack E. Bridges