Patents by Inventor Harsh Garg

Harsh Garg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240364276
    Abstract: Methods, apparatus, systems, and articles of manufacture are described for dynamic digital pre-distortion correction. An example system includes programmable circuitry operable to execute computer readable instructions to at least: generate signal statistics based on an input signal; group the signal statistics into a first group of signal statistics or a second group of signal statistics based on time constants of the signal statistics; decimate the first group of signal statistics; generate a first predistortion term based on the decimated first group of signal statistics; generate a second predistortion term based on the second group of signal statistics; and generate an output predistortion terminal based on the first predistortion term and the second predistortion term.
    Type: Application
    Filed: April 26, 2024
    Publication date: October 31, 2024
    Inventors: Chandrasekhar Sriram, Sarma Sundareswara Gunturi, Jawaharlal Tangudu, Harshit Moondra, Harsh Garg, Sanjay Pennam
  • Publication number: 20240297621
    Abstract: An example method includes switching a first multiplexer circuit associated with first delay circuitry from (a) a first sub-lookup table (LUT) of a first LUT of digital pre-distortion (DPD) corrector circuitry to (b) a first corresponding sub-LUT of a second LUT of the DPD corrector circuitry, the first sub-LUT associated with the first delay circuitry, the second LUT storing updated values to compensate for non-linearity of power amplifier circuitry of a transmitter including the DPD corrector circuitry. The method includes, based on a value of a counter being equal to a difference between (1) a first delay of the first delay circuitry and (2) a second delay of second delay circuitry, switching a second multiplexer circuit associated with the second delay circuitry from (a) a second sub-LUT of the first LUT to (b) a second corresponding sub-LUT of the second LUT, the second sub-LUT associated with the second delay circuitry.
    Type: Application
    Filed: February 29, 2024
    Publication date: September 5, 2024
    Inventors: Jawaharlal Tangudu, Goutham Ramesh, Sarma Sundareswara Gunturi, Harsh Garg, Jaiganesh Balakrishnan, Mathews John, Sashidharan Venkatraman, Sanjay Pennam
  • Patent number: 11356125
    Abstract: An integrated circuit comprises an input, a digital step attenuator, an analog-to-digital converter, a first output, a second output, a first bandwidth filter, a first band attack detector, a first band decay detector, a second bandwidth filter, a second band attack detector, a second band decay detector, and an automatic gain control. The ADC is configured to output a digital signal including a first and a second frequency range. The first and second bandwidth filters are configured to extract respective digital signals comprising the first and second frequency ranges. The band attack and decay detectors are configured to detect band peaks or decays thereof such that the DSA and External AMP may be controlled by means of the AGC based on the detected band peaks or decays, and ADC attack and ADC decay.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: June 7, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jawaharlal Tangudu, Yeswanth Guntupalli, Kalyan Gudipati, Robert Clair Keller, Wenjing Lu, Jaiganesh Balakrishnan, Harsh Garg, Bragadeesh S, Raju Kharataram Chaudhari, Francesco Dantoni
  • Publication number: 20210159924
    Abstract: An integrated circuit comprises an input, a digital step attenuator, an analog-to-digital converter, a first output, a second output, a first bandwidth filter, a first band attack detector, a first band decay detector, a second bandwidth filter, a second band attack detector, a second band decay detector, and an automatic gain control. The ADC is configured to output a digital signal including a first and a second frequency range. The first and second bandwidth filters are configured to extract respective digital signals comprising the first and second frequency ranges. The band attack and decay detectors are configured to detect band peaks or decays thereof such that the DSA and External AMP may be controlled by means of the AGC based on the detected band peaks or decays, and ADC attack and ADC decay.
    Type: Application
    Filed: November 20, 2020
    Publication date: May 27, 2021
    Inventors: Jawaharlal Tangudu, Yeswanth Guntupalli, Kalyan Gudipati, Robert Clair Keller, Wenjing Lu, Jaiganesh Balakrishnan, Harsh Garg, Bragadeesh S, Raju Kharataram Chaudhari, Francesco Dantoni
  • Publication number: 20170349354
    Abstract: A multiple housing vacuum insulated canister to store plurality of liquid. The canister includes a first housing, a second housing, a third housing, a first rotatable lid, and a second rotatable lid. The first housing includes first top end and first bottom end to store first liquid. The second housing stores solid items having second top end and second bottom end. The second top end of second housing is detachably attached with first bottom end. The third housing having a third top end and third bottom end. The third top end of third housing is detachably attached with second bottom end to store second liquid. The first rotatable lid detachably attached with first top end enables access to first liquid. The second rotatable lid detachably attached with third bottom end having adjustable opening level to control flow of second liquid.
    Type: Application
    Filed: June 7, 2016
    Publication date: December 7, 2017
    Applicant: Golchi LLC
    Inventor: Harsh Garg