Abstract: A first in-memory computation (IMC) circuit includes a first IMC processing tile coupled for data communication to a first interface circuit. A second IMC circuit includes a second IMC processing tile coupled for data communication to a second interface circuit. A shared resource bus connects the first and second interface circuits for data communication of feature data, weight data or input computation data.

Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a clamping circuit that clamps a voltage on the bit line to a level exceeding an SRAM cell bit flip voltage during execution of the in-memory compute operation. The column processing circuit may further include a current mirroring circuit that mirrors the read current developed on each bit line in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. The mirrored read current is integrated by an integration capacitor to generate an output voltage that is converted to a digital signal by an analog-to-digital converter circuit.

Abstract: Computational weight data for an in-memory computation operation is stored in a column of memory cells. The in-memory computation operation is executed by actuating word lines connected to the column of memory cells in response to feature data of the in-memory computation operation. An analog signal generated on a bit line of the column is converted, during a converter computation cycle, a digital signal. That digital signal is processed to generate an output of the in-memory computation operation. A randomization signal is generated and applied to control application of a randomized variation to the converter computation cycle. The processing of the digital signal includes adjusting the digital signal to remove error introduced by the random variation applied to the converter computation cycle. The applied random variation affects the power waveform of the in-memory computation device making it more difficult for a power-based side channel attack to succeed.

Abstract: The memory array of a circuit includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports two modes of circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. In memory computation operations are performed in the second mode as a function of feature data and weight data stored in the memory.

Abstract: An in-memory computation circuit includes a memory array including sub-arrays of with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit selectively actuates word lines across the sub-arrays for an in-memory compute operation. A computation tile circuit for each sub-array includes a column compute circuit for each bit line. Each column compute circuit includes a switched timing circuit that is actuated in response to weight data on the bit line for a duration of time set by an in-memory compute operation enable signal. A current digital-to-analog converter powered by the switched timing circuit operates to generate a drain current having a magnitude controlled by bits of feature data for the in-memory compute operation. The drain current is integrated to generate an output voltage.

Abstract: An internal computation clock signal is derived from a clock signal and includes a number of pulses within each clock signal period equal to a number of in-memory computation (IMC) processing tiles of a tile cluster that are included within a stall domain of a neural processing circuit. The pulses of the internal computation clock signal are selectively gated to generate corresponding internal clock signals applied to respective IMC processing tiles of the tile cluster within the stall domain. Timing of IMC processing tile processing operations is controlled by the applied internal clock signal. Data communications output from the IMC processing tiles are time multiplexed over a shared resource bus to a shared compute circuit for processing in response to the internal computation clock signal.

Abstract: A memory system disclosed herein features left and/or right memory banks, with left and/or right input/output (IO) blocks aligned with the memory banks for managing data input and output. A control section, situated between the left and right input/output blocks, oversees memory operations, receives control signals, and performs stuck-at testing. The control section includes fault detection logic designed to output a first logic value (e.g., logic low) if logic values at each of its external inputs are identical, but output a second logic value (e.g., logic high) if not. The fault detection logic is capable of detecting stuck-at faults in the external inputs by performing both stuck-at-0 and stuck-at-1 testing. If only stuck-at-0 or stuck-at-1 faults are detected, the fault detection logic can pinpoint those faults by iteratively changing input values at each of its external inputs and observing the output of the fault detection logic.

Abstract: A first in-memory computation (IMC) circuit includes a first IMC processing tile coupled for data communication to a first interface circuit. A second IMC circuit includes a second IMC processing tile coupled for data communication to a second interface circuit. A shared resource bus connects the first and second interface circuits. The first and second interface circuits are controlled by mode control signals to operate in: a first communications mode where signal lines of the shared resource bus support data communications between the first and second IMC circuits; and a second communications mode where a first subset of signal lines of the shared resource bus support data communications between the first and second IMC circuits and a second, different, subset of signal lines of the shared resource bus are driven to a fixed voltage level to provide shielding for the data communications over the first subset of signal lines.

Abstract: An array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder supports two modes of memory operation: a first mode where only one word line in the memory array is actuated during a read and a second mode where one word line per sub-array are simultaneously actuated during the read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. BIST testing of the input/output circuit is supported through data at both the column data output and the sub-array data outputs in order to confirm proper memory operation in support of both the first and second modes of operation.

Abstract: Various embodiments are directed to example system-on-chip integrated circuits configured to perform built-in self test operations on an embedded memory. An example system-on-chip integrated circuit includes dynamic BIST switching circuitry and an embedded memory. The dynamic BIST switching circuitry is configured to generate a dynamic BIST output based on a test state. The embedded memory is configured to receive the dynamic BIST output. The embedded memory includes fixed BIST switching circuitry configured to generate a fixed BIST output based on the test state. Wherein the fixed BIST switching circuitry is internal to the embedded memory, and the dynamic BIST switching circuitry is external to the embedded memory.

Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a current mirroring circuit that mirrors the read current developed on each bit line in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bias voltage for word line driver and a configuration of the current mirroring circuit to inhibit drop of a voltage on the bit line below a bit flip voltage during execution of the in-memory compute operation. The mirrored read current is integrated by an integration capacitor to generate an output voltage that is converted to a digital signal by an analog-to-digital converter circuit.

Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a read circuit that operates to reduce sensitivity to variation in bit line read current. Additionally, a testing circuit senses analog signals on the complementary bit lines to identify one of the complementary bit lines as having a less variable read current. That identified one of the complementary bit lines is coupled to the read circuit for the in-memory compute operation.

Abstract: Disclosed herein is a self-timed memory circuit with a bypass mode for testing output shadow logic. The circuit is applicable to various memory types, including ROM, HistoRAM, and TCAM. In normal operation, the memory array outputs data through sense amplifiers and latches, controlled by self-timing circuitry. The output then passes through shadow logic for additional processing. The bypass mode allows direct testing of the shadow logic by inputting test patterns (address bits or search keys) that bypass the memory array. These test signals use the same self-timing mechanisms as normal operations, providing for accurate timing representation. This approach enhances fault coverage for shadow logic, enabling detection of transient faults and at-speed errors that might be missed by conventional static testing.

Abstract: When a mode control signal indicates performance of an in-memory computation operation with a P-bit precision, a P-bit precision multiplier multiplies P-bits of feature data by P-bits of weight data to produce a computation output within one cycle of a clock signal. When the mode control signal indicates performance of the in-memory computation operation with a Q-bit precision, where Q=x*P, Q-bits of feature data are divided into P-bit blocks, the P-bit precision multiplier multiplies each P-bit block by P-bits of weight data in response to each pulse of an internal clock pulse, and the multiplication results are summed to produce the computation output within one cycle of a clock signal. A clock generator circuit generates x internal clock pulses for each cycle of the clock signal.

Abstract: A memory array includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports: a first mode where only one word line in the memory array is actuated during a column multiplexed memory access operation; and a second mode where one word line per sub-array is simultaneously actuated during an in-memory computation operation. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs to provide data read from the array in the first mode, and a sub-array data output coupled to each bit line input to provide weight data read from the array in the second mode. A computational circuit executes the in-memory computation as a function of feature data and the read weight data.

Abstract: Computational weight data for an in-memory computation operation is stored in memory cells of a memory array. During execution of the in-memory computation operation, the computational weight data is read from the memory array using a randomly selected order of row and/or column access. A digital computation processing circuit receives feature data for the in-memory computation operation and performs a computational operation as a function of the feature data and the read computational weight data. A map signal generated in response to the memory access provides information specifying the randomly scrambled order of access. the digital computation processing circuit uses that information to map the retrieved computational weight data to the feature data when performing the computational operation for the in-memory computation operation.

Abstract: A memory circuit includes an address port, a data input port and a data output port. An upstream shadow logic circuit is coupled to provide address data to the address port of the memory circuit and input data to the data input port of the memory circuit. A downstream shadow logic circuit is coupled to receive output data from the data output port of the memory circuit. The memory circuit includes a bypass path between the address port and the data output port. This bypass path is activated during a testing operation to pass bits of the address data (forming test data) applied by upstream shadow logic circuit from the address port to the data output port.

Abstract: A circuit memory includes sub-arrays with memory cells (storing weight data for an in-memory computation operation) arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. For in-memory computation operation execution, a control circuit simultaneously actuates one word line per sub-array. An input/output circuit for each column includes bit line inputs to the local bit lines of the sub-arrays and a sub-array data output coupled to each bit line input. Bit lines of the sub-arrays in a dummy column of the memory are precharged to a randomly selected one of first and second voltage levels in connection with execution of the in-memory computation operation to provide a randomization of circuit power consumption as a measure to protect the memory from a side channel attack to extract the weight data.

Abstract: Computational weight data for an in-memory computation operation is written to memory cells in a memory array with a randomly selected polarity inversion. During execution of the in-memory computation operation, the computational weight data is read from memory cells in the memory array. A polarity inversion is applied to the read computational weight data when that read computational weight data was written to memory cells in the memory array with the randomly selected polarity inversion.

Abstract: First and second in-memory computation (IMC) processing tiles store computational weight data for in-memory computation operations executed in response to feature data. The first IMC processing tile is clocked by a first clock signal to control execution of the in-memory computation operation, and the second IMC processing tile is clocked by a second clock signal to control execution of the in-memory computation operation. A clock tree generates the first and second clock signals. In response to a random number, the clock tree applies a randomized stagger to timing of the first and second clock signals. A binding circuit matches and binds the first and second computation outputs. The binding circuit, in response to the random number, accounts for timing offset between the first and second computation outputs due to the randomized stagger to timing of the first and second clock signals.