Patents by Inventor Harsh Sharma

Harsh Sharma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080040382
    Abstract: A method for selecting members in a hierarchy includes determining a sequence of one or more actions associated with a member selection tree. The actions collectively selecting one or more members from a hierarchy of members. The hierarchy of members is associated with a particular dimension of an organization of data. The method further includes recording the sequence of actions in a member selection script. In addition, the method includes executing the member selection script to select one or more members after the hierarchy of members has been modified.
    Type: Application
    Filed: October 23, 2007
    Publication date: February 14, 2008
    Inventors: Richard Morris, Marc Skinner, Harsh Sharma
  • Patent number: 7324983
    Abstract: A method for selecting members in a hierarchy includes determining a sequence of one or more actions associated with a member selection tree. The actions collectively selecting one or more members from a hierarchy of members. The hierarchy of members is associated with a particular dimension of an organization of data. The method further includes recording the sequence of actions in a member selection script. In addition, the method includes executing the member selection script to select one or more members after the hierarchy of members has been modified.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: January 29, 2008
    Assignee: i2 Technologies US, Inc.
    Inventors: Richard A. Morris, Marc P. Skinner, Harsh Sharma
  • Patent number: 7034576
    Abstract: A circuit has been developed that reduces the effective strength of a keeper circuit during an interval in which at least one path of an evaluation circuit is sensitive to a keeper device. The keeper circuit includes a keeper gating device coupled to a keeper device that is responsive to a keeper control. The keeper device is sized to overcome leakage current in the evaluation circuit. In some configurations, the keeper circuit includes a weak keeper device that is minimally sized to overcome noise while the keeper device is effectively disabled. In some configurations, the reduction in effective strength of the keeper circuit occurs before arrival of the fastest signal coupled to a sensitive output path of the evaluation circuit and the effective strength is restored after arrival of the slowest signal coupled to the sensitive output path of the evaluation circuit.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: April 25, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Howard Levy, Nadeem Eleyan, Harsh Sharma, Hong Kim
  • Publication number: 20040263208
    Abstract: A circuit has been developed that reduces the effective strength of a keeper circuit during an interval in which at least one path of an evaluation circuit is sensitive to a keeper device. The keeper circuit includes a keeper gating device coupled to a keeper device that is responsive to a keeper control. The keeper device is sized to overcome leakage current in the evaluation circuit. In some configurations, the keeper circuit includes a weak keeper device that is minimally sized to overcome noise while the keeper device is effectively disabled. In some configurations, the reduction in effective strength of the keeper circuit occurs before arrival of the fastest signal coupled to a sensitive output path of the evaluation circuit and the effective strength is restored after arrival of the slowest signal coupled to the sensitive output path of the evaluation circuit.
    Type: Application
    Filed: June 27, 2003
    Publication date: December 30, 2004
    Applicant: Sun Microsystems, Inc.
    Inventors: Howard Levy, Nadeem Eleyan, Harsh Sharma, Hong Kim
  • Patent number: 6819138
    Abstract: Devices, methods, and networks that divide and proportionally distribute the drive strength of a clock buffer such that the output drive strength of the clock buffer is divided proportionally among a plurality of outputs from the clock buffer. In one embodiment, the present invention selectively couples adjacent parallel inverters present in a clock buffer to separate, internal distribution wires. The internal distribution wires are selectively coupled to one or more outputs by a connector wire to provide proportional, multiple outputs of the drive strength from the clock buffer to a clock network.
    Type: Grant
    Filed: November 4, 2002
    Date of Patent: November 16, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: David Hogenmiller, Harsh Sharma, Shervin Hojat
  • Patent number: 6789245
    Abstract: Coupling capacitance is used to balance skew in a network. In one embodiment, the coupling capacitance exerted by shielding wires oppositely adjacent one or more signal wires in a network is utilized to vary the speed of a signal carried on the one or more signal wires to balance skew in the network.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: September 7, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Shervin Hojat, David Hogenmiller, Harsh Sharma
  • Publication number: 20040085094
    Abstract: Devices, methods, and networks that divide and proportionally distribute the drive strength of a clock buffer such that the output drive strength of the clock buffer is divided proportionally among a plurality of outputs from the clock buffer. In one embodiment, the present invention selectively couples adjacent parallel inverters present in a clock buffer, to separate, internal distribution wires. The internal distribution wires are selectively coupled to one or more outputs by a connector wire to provide proportional, multiple outputs of the drive strength from the clock buffer to a clock network.
    Type: Application
    Filed: November 4, 2002
    Publication date: May 6, 2004
    Applicant: Sun Microsystems, Inc.
    Inventors: David Hogenmiller, Harsh Sharma, Shervin Hojat
  • Publication number: 20040078773
    Abstract: Predetermined and standardized path templates are introduced between points and/or elements in an integrated circuit layout. According to one embodiment of the invention, the standardized path templates are made up of two or more parallel tracks of path segments, with or without corresponding perpendicular path segments. According to the invention, the path segments are connected as needed to form serpentine or non-serpentine paths of the required length.
    Type: Application
    Filed: October 21, 2002
    Publication date: April 22, 2004
    Applicant: Sun Microsystems, Inc.
    Inventors: Harsh Sharma, Shervin Hojat, David Hogenmiller
  • Publication number: 20040068709
    Abstract: Coupling capacitance is used to balance skew in a network. In one embodiment, the coupling capacitance exerted by shielding wires oppositely adjacent one or more signal wires in a network is utilized to vary the speed of a signal carried on the one or more signal wires to balance skew in the network.
    Type: Application
    Filed: October 8, 2002
    Publication date: April 8, 2004
    Applicant: Sun Microsystems, Inc.
    Inventors: Shervin Hojat, David Hogenmiller, Harsh Sharma
  • Patent number: 6684372
    Abstract: Provided is a method, a system and a computer product to translate electronic schematic files between computer-aided software design tools. One embodiment of the invention includes converting source files, containing electronic schematic information, into output files. Creating, from the source files, export files that omit a sub-portion of the schematic information, defining omitted data, each of the export files having a file name associated therewith. Appending, to the file name of the export files, data concerning the omitted information to form an appended file name. The export files are converted to the output files retained in the appended file name. The appended name is diminished so as to remove all information therefrom, excepting information corresponding to the omitted information.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: January 27, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Sze Tom, Harsh Sharma, Kong-Fai Woo
  • Publication number: 20030177456
    Abstract: Provided is a method, a system and a computer product to translate electronic schematic files between computer-aided software design tools. One embodiment of the invention includes converting source files, containing electronic schematic information, into output files. Creating, from the source files, export files that omit a sub-portion of the schematic information, defining omitted data, each of the export files having a file name associated therewith. Appending, to the file name of the export files, data concerning the omitted information to form an appended file name. The export files are converted to the output files retained in the appended file name. The appended name is diminished so as to remove all information therefrom, excepting information corresponding to the omitted information.
    Type: Application
    Filed: March 15, 2002
    Publication date: September 18, 2003
    Applicant: SUN MICROSYSTEMS, INC.
    Inventors: Sze Tom, Harsh Sharma, Kong-Fai Woo
  • Patent number: 6111455
    Abstract: A method for controlling delays in silicon on insulator circuits is disclosed. A semiconductor integrated circuit device comprises a first circuit and a second circuit. The first circuit includes multiple transistors, some of which have a floating body. In addition, the first circuit includes an input and an output. The second circuit is selectively coupled to a floating body of some of the transistors in the first circuit in order to control the delay of the output of the first circuit.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: August 29, 2000
    Assignee: International Business Machines Corporation
    Inventors: Nadeem Eleyan, Harsh Sharma