Abstract: Devices, methods, and networks that divide and proportionally distribute the drive strength of a clock buffer such that the output drive strength of the clock buffer is divided proportionally among a plurality of outputs from the clock buffer. In one embodiment, the present invention selectively couples adjacent parallel inverters present in a clock buffer to separate, internal distribution wires. The internal distribution wires are selectively coupled to one or more outputs by a connector wire to provide proportional, multiple outputs of the drive strength from the clock buffer to a clock network.

Abstract: Coupling capacitance is used to balance skew in a network. In one embodiment, the coupling capacitance exerted by shielding wires oppositely adjacent one or more signal wires in a network is utilized to vary the speed of a signal carried on the one or more signal wires to balance skew in the network.

Abstract: Devices, methods, and networks that divide and proportionally distribute the drive strength of a clock buffer such that the output drive strength of the clock buffer is divided proportionally among a plurality of outputs from the clock buffer. In one embodiment, the present invention selectively couples adjacent parallel inverters present in a clock buffer, to separate, internal distribution wires. The internal distribution wires are selectively coupled to one or more outputs by a connector wire to provide proportional, multiple outputs of the drive strength from the clock buffer to a clock network.

Abstract: Predetermined and standardized path templates are introduced between points and/or elements in an integrated circuit layout. According to one embodiment of the invention, the standardized path templates are made up of two or more parallel tracks of path segments, with or without corresponding perpendicular path segments. According to the invention, the path segments are connected as needed to form serpentine or non-serpentine paths of the required length.

Abstract: Coupling capacitance is used to balance skew in a network. In one embodiment, the coupling capacitance exerted by shielding wires oppositely adjacent one or more signal wires in a network is utilized to vary the speed of a signal carried on the one or more signal wires to balance skew in the network.

Abstract: Provided is a method, a system and a computer product to translate electronic schematic files between computer-aided software design tools. One embodiment of the invention includes converting source files, containing electronic schematic information, into output files. Creating, from the source files, export files that omit a sub-portion of the schematic information, defining omitted data, each of the export files having a file name associated therewith. Appending, to the file name of the export files, data concerning the omitted information to form an appended file name. The export files are converted to the output files retained in the appended file name. The appended name is diminished so as to remove all information therefrom, excepting information corresponding to the omitted information.

Abstract: Provided is a method, a system and a computer product to translate electronic schematic files between computer-aided software design tools. One embodiment of the invention includes converting source files, containing electronic schematic information, into output files. Creating, from the source files, export files that omit a sub-portion of the schematic information, defining omitted data, each of the export files having a file name associated therewith. Appending, to the file name of the export files, data concerning the omitted information to form an appended file name. The export files are converted to the output files retained in the appended file name. The appended name is diminished so as to remove all information therefrom, excepting information corresponding to the omitted information.

Abstract: A method for controlling delays in silicon on insulator circuits is disclosed. A semiconductor integrated circuit device comprises a first circuit and a second circuit. The first circuit includes multiple transistors, some of which have a floating body. In addition, the first circuit includes an input and an output. The second circuit is selectively coupled to a floating body of some of the transistors in the first circuit in order to control the delay of the output of the first circuit.