Patents by Inventor Harsha Gupta
Harsha Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250117319Abstract: A method includes receiving, via a communication link and at a device of an integrated circuit system, a cache line comprising a destination address, determining, via the device, a type of memory or storage associated with the destination address, the type of memory or storage comprising persistent or non-persistent, and tagging the cache line with metadata in a manner indicating the type of memory or storage associated with the destination address.Type: ApplicationFiled: December 19, 2024Publication date: April 10, 2025Inventors: Sharath Raghava, Nagabhushan Chitlur, Harsha Gupta
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Patent number: 12237831Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.Type: GrantFiled: May 16, 2023Date of Patent: February 25, 2025Assignee: Intel CorporationInventors: Sharath Raghava, Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad, Sean R. Atsatt
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Patent number: 12204441Abstract: A method includes receiving, via a communication link and at a device of an integrated circuit system, a cache line comprising a destination address, determining, via the device, a type of memory or storage associated with the destination address, the type of memory or storage comprising persistent or non-persistent, and tagging the cache line with metadata in a manner indicating the type of memory or storage associated with the destination address.Type: GrantFiled: December 24, 2020Date of Patent: January 21, 2025Assignee: Altera CorporationInventors: Sharath Raghava, Nagabhushan Chitlur, Harsha Gupta
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Publication number: 20240338397Abstract: Methods, apparatus, systems, and articles of manufacture to determine a number of denoising iterations of model output generation are disclosed. An example apparatus includes at least one programmable circuit to execute a model to generate a plurality of outputs based on a text-based prompt, each of the plurality of outputs generated using different numbers of denoising iterations; generate an ordered set of the plurality of outputs based on the number of denoising iterations; determine a plurality of similarities between neighboring outputs in the ordered set of the plurality of outputs; and select a number of denoising iterations based on the plurality of similarities.Type: ApplicationFiled: June 17, 2024Publication date: October 10, 2024Inventors: Jean Xu Yu, Haim Shmuel Barad, Harsha Gupta
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Publication number: 20240028544Abstract: An integrated circuit device may include a first network on chip (NOC) circuit configured to receive a set of data and transfer the set of data to a first node of the first NOC circuitry. The first node is configured to transfer the set of data to a second NOC circuit of an additional integrated circuit device separate from the integrated circuit device.Type: ApplicationFiled: September 29, 2023Publication date: January 25, 2024Inventors: Sharath Raghava, Dheeraj Subbareddy, Kavitha Prasad, Ankireddy Nalamalpu, Harsha Gupta
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Publication number: 20230370068Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.Type: ApplicationFiled: May 16, 2023Publication date: November 16, 2023Inventors: Sharath Raghava, Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad, Sean R. Atsatt
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Patent number: 11789883Abstract: An integrated circuit device may include a first network on chip (NOC) circuit configured to receive a set of data and transfer the set of data to a first node of the first NOC circuitry. The first node is configured to transfer the set of data to a second NOC circuit of an additional integrated circuit device separate from the integrated circuit device.Type: GrantFiled: August 14, 2018Date of Patent: October 17, 2023Assignee: INTEL CORPORATIONInventors: Sharath Raghava, Dheeraj Subbareddy, Kavitha Prasad, Ankireddy Nalamalpu, Harsha Gupta
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Patent number: 11700002Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.Type: GrantFiled: December 20, 2021Date of Patent: July 11, 2023Assignee: Intel CorporationInventors: Sharath Raghava, Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad, Sean R. Atsatt
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Patent number: 11342918Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.Type: GrantFiled: September 25, 2020Date of Patent: May 24, 2022Assignee: Intel CorporationInventors: Sharath Raghava, Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad, Sean R. Atsatt
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Publication number: 20220116044Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.Type: ApplicationFiled: December 20, 2021Publication date: April 14, 2022Inventors: Sharath Raghava, Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad, Sean R. Atsatt
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Patent number: 11206024Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.Type: GrantFiled: September 25, 2020Date of Patent: December 21, 2021Assignee: Intel CorporationInventors: Sharath Raghava, Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad, Sean R. Atsatt
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Publication number: 20210182187Abstract: A method includes receiving, via a communication link and at a device of an integrated circuit system, a cache line comprising a destination address, determining, via the device, a type of memory or storage associated with the destination address, the type of memory or storage comprising persistent or non-persistent, and tagging the cache line with metadata in a manner indicating the type of memory or storage associated with the destination address.Type: ApplicationFiled: December 24, 2020Publication date: June 17, 2021Inventors: Sharath Raghava, Nagabhushan Chitlur, Harsha Gupta
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Publication number: 20210013887Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.Type: ApplicationFiled: September 25, 2020Publication date: January 14, 2021Inventors: Sharath Raghava, Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad, Sean R. Atsatt
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Patent number: 10790827Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.Type: GrantFiled: December 27, 2018Date of Patent: September 29, 2020Assignee: Intel CorporationInventors: Sharath Raghava, Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad, Sean R. Atsatt
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Patent number: 10649927Abstract: A central processing unit (CPU) may be directly coupled to an accelerator dual in-line memory module (DIMM) card that is plugged into a DIMM slot. The CPU may include a master memory controller that sends requests or offloads tasks to the accelerator DIMM card via a low-latency double data rate (DDR) interface. The acceleration DIMM card may include a slave memory controller for translating the received requests, a decoder for decoding the translated requests, control circuitry for orchestrating the data flow within the DIMM card, hardware acceleration resources that can be dynamically programmed to support a wide variety of custom functions, and input-output components for interfacing with various types of non-volatile and/or volatile memory and for connecting with other types of storage and processing devices.Type: GrantFiled: December 6, 2018Date of Patent: May 12, 2020Assignee: Intel CorporationInventors: Sharath Raghava, Dheeraj Subbareddy, Kavitha Prasad, Ankireddy Nalamalpu, Harsha Gupta
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Publication number: 20190131975Abstract: Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.Type: ApplicationFiled: December 27, 2018Publication date: May 2, 2019Inventors: Sharath Raghava, Ankireddy Nalamalpu, Dheeraj Subbareddy, Harsha Gupta, James Ball, Kavitha Prasad, Sean R. Atsatt
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Publication number: 20190108145Abstract: A central processing unit (CPU) may be directly coupled to an accelerator dual in-line memory module (DIMM) card that is plugged into a DIMM slot. The CPU may include a master memory controller that sends requests or offloads tasks to the accelerator DIMM card via a low-latency double data rate (DDR) interface. The acceleration DIMM card may include a slave memory controller for translating the received requests, a decoder for decoding the translated requests, control circuitry for orchestrating the data flow within the DIMM card, hardware acceleration resources that can be dynamically programmed to support a wide variety of custom functions, and input-output components for interfacing with various types of non-volatile and/or volatile memory and for connecting with other types of storage and processing devices.Type: ApplicationFiled: December 6, 2018Publication date: April 11, 2019Applicant: Intel CorporationInventors: Sharath Raghava, Dheeraj Subbareddy, Kavitha Prasad, Ankireddy Nalamalpu, Harsha Gupta
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Publication number: 20190050361Abstract: An integrated circuit device may include a first network on chip (NOC) circuit configured to receive a set of data and transfer the set of data to a first node of the first NOC circuitry. The first node is configured to transfer the set of data to a second NOC circuit of an additional integrated circuit device separate from the integrated circuit device.Type: ApplicationFiled: August 14, 2018Publication date: February 14, 2019Inventors: Sharath Raghava, Dheeraj Subbareddy, Kavitha Prasad, Ankireddy Nalamalpu, Harsha Gupta