Patents by Inventor Harsha Narasimha Acharya

Harsha Narasimha Acharya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Error detection for a wireless channel
    Patent number: 11152953
    Abstract: Methods, systems, and devices for wireless communications are described. In some systems, a first device may transmit a signal to a second device including a number of error detection bits interleaved with a number of information bits. The second device may use the error detection bits to determine if the signal was received correctly, where each error detection bit may be associated with a set of information bits. The second device may progressively decode the signal and continuously perform an error detection calculation based on a first set of information bits associated with a first error detection bit. Based on the error detection calculation, the second device may calculate an expected error detection bit corresponding to the first error detection bit. The second device may compare the first error detection bit to the expected error detection bit. Other aspects and features are also claimed and described.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: October 19, 2021
    Assignee: QUALCOMM INCORPORATED
    Inventors: Afshin Haftbaradaran, Ming Ta Lin, Shravan Kumar Reddy Garlapati, Alessandro Risso, Alexandre Pierrot, Harsha Narasimha Acharya, Subramanya Rao, Li Zhang
  • ERROR DETECTION FOR A WIRELESS CHANNEL
    Publication number: 20210273651
    Abstract: Methods, systems, and devices for wireless communications are described. In some systems, a first device may transmit a signal to a second device including a number of error detection bits interleaved with a number of information bits. The second device may use the error detection bits to determine if the signal was received correctly, where each error detection bit may be associated with a set of information bits. The second device may progressively decode the signal and continuously perform an error detection calculation based on a first set of information bits associated with a first error detection bit. Based on the error detection calculation, the second device may calculate an expected error detection bit corresponding to the first error detection bit. The second device may compare the first error detection bit to the expected error detection bit. Other aspects and features are also claimed and described.
    Type: Application
    Filed: February 28, 2020
    Publication date: September 2, 2021
    Inventors: Afshin Haftbaradaran, Ming Ta Lin, Shravan Kumar Reddy Garlapati, Alessandro Risso, Alexandre Pierrot, Harsha Narasimha Acharya, Subramanya Rao, Li Zhang