Abstract: Circuitry comprises ray tracing circuitry comprising a plurality of floating-point circuitries to perform floating-point processing operations to detect intersection between a virtual ray defined by a ray direction and a test region, the floating-point circuitries operating to a given precision to generate an output floating-point value comprising a significand and an exponent; in which at least some of the plurality of floating-point circuitries are configured to round using a predetermined directed rounding mode any denormal floating-point value generated by operation of that circuitry so as to output normal values, a denormal floating-point value being a floating-point value in which the significand comprises one or more leading zeroes.

Abstract: Apparatus, method and non-transitory computer-readable medium to store computer-readable code for fabrication of an apparatus. The apparatus comprises instruction decode circuitry to decode instructions and processing circuitry to execute the instructions decoded by the instruction decode circuitry.

Abstract: A data processing apparatus is provided. An A×B multiplier array has a group of logic gates clocked by a first clock signal, where A and B are both integers. A C×D multiplier array, separate from the A×B multiplier array, has second group of logic gates clocked by a second clock signal, where C and D are both integers. Addition circuitry performs an addition operation between a first at least partial product produced by the A×B multiplier array and a second at least partial product produced by the C×D multiplier array.

Abstract: An apparatus comprises floating-point processing circuitry to perform a floating-point operation with rounding to generate a floating-point result value; and tininess detection circuitry to detect a tininess status indicating whether an outcome of the floating-point operation is tiny. A tiny outcome corresponds to a non-zero number with a magnitude smaller than a minimum non-zero magnitude representable as a normal floating-point number in a floating-point format to be used for the floating-point result value. The tininess detection circuitry comprises hardware circuit logic configured to support both before rounding tininess detection and after rounding tininess detection for detecting the tininess status.

Abstract: Circuitry comprises ray tracing circuitry comprising a plurality of floating-point circuitries to perform floating-point processing operations to detect intersection between a virtual ray defined by a ray direction and a test region, the floating-point circuitries operating to a given precision to generate an output floating-point value comprising a significand and an exponent; in which at least some of the plurality of floating-point circuitries are configured to round using a predetermined directed rounding mode any denormal floating-point value generated by operation of that circuitry so as to output normal values, a denormal floating-point value being a floating-point value in which the significand comprises one or more leading zeroes.