Patents by Inventor Harshavardhan Kaushikkar
Harshavardhan Kaushikkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11947457Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.Type: GrantFiled: November 22, 2022Date of Patent: April 2, 2024Assignee: Apple Inc.Inventors: James Vash, Gaurav Garg, Brian P. Lilly, Ramesh B. Gunna, Steven R. Hutsell, Lital Levy-Rubin, Per H. Hammarlund, Harshavardhan Kaushikkar
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Patent number: 11941428Abstract: Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include one or more queues and a transaction pipeline. The I/O agent circuit may issue, to the transaction pipeline from a queue of the one or more queues, a transaction of a series of transactions enqueued in a particular order. The I/O agent circuit may generate, at the transaction pipeline, a determination to return the transaction to the queue based on a detection of one or more conditions being satisfied. Based on the determination, the I/O agent circuit may reject, at the transaction pipeline, up to a threshold number of transactions that issued from the queue after the transaction issued. The I/O agent circuit may insert the transaction at a head of the queue such that the transaction is enqueued at the queue sequentially first for the series of transactions according to the particular order.Type: GrantFiled: March 31, 2022Date of Patent: March 26, 2024Assignee: Apple Inc.Inventors: Sagi Lahav, Lital Levy-Rubin, Gaurav Garg, Gerard R. Williams, III, Samer Nassar, Per H. Hammarlund, Harshavardhan Kaushikkar, Srinivasa Rangan Sridharan, Jeff Gonion
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Patent number: 11934313Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.Type: GrantFiled: August 22, 2022Date of Patent: March 19, 2024Assignee: Apple Inc.Inventors: Per H. Hammarlund, Lior Zimet, James Vash, Gaurav Garg, Sergio Kolor, Harshavardhan Kaushikkar, Ramesh B. Gunna, Steven R. Hutsell
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Patent number: 11868258Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.Type: GrantFiled: January 27, 2023Date of Patent: January 9, 2024Assignee: Apple Inc.Inventors: James Vash, Gaurav Garg, Brian P. Lilly, Ramesh B. Gunna, Steven R. Hutsell, Lital Levy-Rubin, Per H. Hammarlund, Harshavardhan Kaushikkar
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Patent number: 11824795Abstract: Techniques are disclosed relating to merging virtual communication channels in a portion of a computing system. In some embodiments, a communication fabric routes first and second classes of traffic with different quality-of-service parameters, using a first virtual channel for the first class and a second virtual channel for the second class. In some embodiments, a memory controller communicates, via the fabric, using a merged virtual channel configured to handle traffic from both the first virtual channel and the second virtual channel. In some embodiments, the system limits the rate at which an agent is allowed to transmit requests of the second class of traffic, but requests by the agent for the first class of traffic are not rate limited. Disclosed techniques may improve independence of virtual channels, relative to sharing the same channel in an entire system, without unduly increasing complexity.Type: GrantFiled: November 17, 2021Date of Patent: November 21, 2023Inventors: Rohit K. Gupta, Gregory S. Mathews, Harshavardhan Kaushikkar, Jeonghee Shin, Rohit Natarajan
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Publication number: 20230367510Abstract: In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.Type: ApplicationFiled: May 16, 2023Publication date: November 16, 2023Inventors: Steven Fishwick, Lior Zimet, Harshavardhan Kaushikkar
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Publication number: 20230350828Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.Type: ApplicationFiled: April 28, 2023Publication date: November 2, 2023Inventors: Sergio Kolor, Sergio V. Tota, Tzach Zemer, Sagi Lahav, Jonathan M. Redshaw, Per H. Hammarlund, Eran Tamari, James Vash, Gaurav Garg, Lior Zimet, Harshavardhan Kaushikkar, Steven Fishwick, Steven R. Hutsell, Shawn M. Fukami
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Patent number: 11803471Abstract: An integrated circuit (IC) including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. For example, the IC may include an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices; and an off-chip interconnect coupled to the interconnect fabric and configured to couple the interconnect fabric to a corresponding interconnect fabric on another instance of the integrated circuit, wherein the interconnect fabric and the off-chip interconnect provide an interface that transparently connects the one or more memory controller circuits, the processor cores, graphics processing units, and peripheral devices in either a single instance of the integrated circuit or two or more instances of the integrated circuit.Type: GrantFiled: August 22, 2022Date of Patent: October 31, 2023Assignee: Apple Inc.Inventors: Per H. Hammarlund, Lior Zimet, Sergio Kolor, Sagi Lahav, James Vash, Gaurav Garg, Tal Kuzi, Jeffry E. Gonion, Charles E. Tucker, Lital Levy-Rubin, Dany Davidov, Steven Fishwick, Nir Leshem, Mark Pilip, Gerard R. Williams, III, Harshavardhan Kaushikkar, Srinivasa Rangan Sridharan
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Publication number: 20230325086Abstract: A memory controller may include a dynamic arbitration scheme to dynamically vary arbitration factors of two or more traffic classes based on dynamic latency tolerance, requested and available bandwidths on an interconnect from source agents to memory controllers, and other dynamic and static factors.Type: ApplicationFiled: August 31, 2022Publication date: October 12, 2023Inventors: Anjana Subramanian, Rohit Natarajan, Yu Simon Zhang, Mukul A. Joshi, Harshavardhan Kaushikkar, Jeonghee Shin, Srinivasa Rangan Sridharan
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Patent number: 11755489Abstract: A configurable interface circuit is disclosed. An integrated circuit (IC) having a particular configuration. The IC includes a memory system and a communication fabric coupled to the memory system. The IC further includes a plurality of agent circuits configured to make requests to the memory system that are in a first format that is not specific to the particular configuration of the IC. A plurality of interface circuits is coupled between corresponding ones of the plurality of agent circuits and the communication fabric. A given one of the plurality of interface circuits is configured to receive a request to the memory system in the first format and output the request in a second format that is specific to the particular configuration of the IC.Type: GrantFiled: August 31, 2021Date of Patent: September 12, 2023Assignee: Apple Inc.Inventors: Rohit K. Gupta, Rohit Natarajan, Jurgen M. Schulz, Harshavardhan Kaushikkar, Connie W. Cheung
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Patent number: 11693585Abstract: In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.Type: GrantFiled: June 21, 2021Date of Patent: July 4, 2023Assignee: Apple Inc.Inventors: Steven Fishwick, Lior Zimet, Harshavardhan Kaushikkar
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Patent number: 11675722Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.Type: GrantFiled: June 3, 2021Date of Patent: June 13, 2023Assignee: Apple Inc.Inventors: Sergio Kolor, Sergio V. Tota, Tzach Zemer, Sagi Lahav, Jonathan M. Redshaw, Per H. Hammarlund, Eran Tamari, James Vash, Gaurav Garg, Lior Zimet, Harshavardhan Kaushikkar, Steven Fishwick, Steven R. Hutsell, Shawn M. Fukami
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Publication number: 20230169003Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.Type: ApplicationFiled: January 27, 2023Publication date: June 1, 2023Inventors: James Vash, Gaurav Garg, Brian P. Lilly, Ramesh B. Gunna, Steven R. Hutsell, Lital Levy-Rubin, Per H. Hammarlund, Harshavardhan Kaushikkar
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Publication number: 20230083397Abstract: A scalable cache coherency protocol for system including a plurality of coherent agents coupled to one or more memory controllers is described. The memory controller may implement a precise directory for cache blocks from the memory to which the memory controller is coupled. Multiple requests to a cache block may be outstanding, and snoops and completions for requests may include an expected cache state at the receiving agent, as indicated by a directory in the memory controller when the request was processed, to allow the receiving agent to detect race conditions. In an embodiment, the cache states may include a primary shared and a secondary shared state. The primary shared state may apply to a coherent agent that bears responsibility for transmitting a copy of the cache block to a requesting agent. In an embodiment, at least two types of snoops may be supported: snoop forward and snoop back.Type: ApplicationFiled: November 22, 2022Publication date: March 16, 2023Inventors: James Vash, Gaurav Garg, Brian P. Lilly, Ramesh B. Gunna, Steven R. Hutsell, Lital Levy-Rubin, Per H. Hammarlund, Harshavardhan Kaushikkar
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Publication number: 20230064369Abstract: A configurable interface circuit is disclosed. An integrated circuit (IC) having a particular configuration. The IC includes a memory system and a communication fabric coupled to the memory system. The IC further includes a plurality of agent circuits configured to make requests to the memory system that are in a first format that is not specific to the particular configuration of the IC. A plurality of interface circuits is coupled between corresponding ones of the plurality of agent circuits and the communication fabric. A given one of the plurality of interface circuits is configured to receive a request to the memory system in the first format and output the request in a second format that is specific to the particular configuration of the IC.Type: ApplicationFiled: August 31, 2021Publication date: March 2, 2023Inventors: Rohit K. Gupta, Rohit Natarajan, Jurgen M. Schulz, Harshavardhan Kaushikkar, Connie W. Cheung
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Publication number: 20230063676Abstract: Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include a transaction pipeline and a pool of counters. The I/O agent circuit may initialize a first counter included in the pool of counters with an initial counter value. The I/O agent circuit may assign the first counter to a specific transaction type. The I/O agent circuit may increment the first counter as a part of allocating a transaction of a transaction type included in a set of transaction types different than the specific transaction type. Based on receiving a transaction request to process a first transaction of the specific transaction type, the I/O agent circuit may bind the first transaction to the first counter. The I/O agent circuit may issue the first transaction to the transaction pipeline based on a counter value stored by the first counter matching the initial counter value.Type: ApplicationFiled: March 31, 2022Publication date: March 2, 2023Inventors: Sagi Lahav, Lital Levy - Rubin, Gaurav Garg, Gerard R. Williams, III, Samer Nassar, Per H. Hammarlund, Harshavardhan Kaushikkar, Srinivasa Rangan Sridharan, Jeff Gonion
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Publication number: 20230064526Abstract: Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include one or more queues and a transaction pipeline. The I/O agent circuit may issue, to the transaction pipeline from a queue of the one or more queues, a transaction of a series of transactions enqueued in a particular order. The I/O agent circuit may generate, at the transaction pipeline, a determination to return the transaction to the queue based on a detection of one or more conditions being satisfied. Based on the determination, the I/O agent circuit may reject, at the transaction pipeline, up to a threshold number of transactions that issued from the queue after the transaction issued. The I/O agent circuit may insert the transaction at a head of the queue such that the transaction is enqueued at the queue sequentially first for the series of transactions according to the particular order.Type: ApplicationFiled: March 31, 2022Publication date: March 2, 2023Inventors: Sagi Lahav, Lital Levy - Rubin, Gaurav Garg, Gerard R. Williams, III, Samer Nassar, Per H. Hammarlund, Harshavardhan Kaushikkar, Srinivasa Rangan Sridharan, Jeff Gonion
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Publication number: 20230064187Abstract: Techniques are disclosed relating to merging virtual communication channels in a portion of a computing system. In some embodiments, a communication fabric routes first and second classes of traffic with different quality-of-service parameters, using a first virtual channel for the first class and a second virtual channel for the second class. In some embodiments, a memory controller communicates, via the fabric, using a merged virtual channel configured to handle traffic from both the first virtual channel and the second virtual channel. In some embodiments, the system limits the rate at which an agent is allowed to transmit requests of the second class of traffic, but requests by the agent for the first class of traffic are not rate limited. Disclosed techniques may improve independence of virtual channels, relative to sharing the same channel in an entire system, without unduly increasing complexity.Type: ApplicationFiled: November 17, 2021Publication date: March 2, 2023Inventors: Rohit K. Gupta, Gregory S. Mathews, Harshavardhan Kaushikkar, Jeonghee Shin, Rohit Natarajan
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Publication number: 20230053530Abstract: A system including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture.Type: ApplicationFiled: August 22, 2022Publication date: February 23, 2023Inventors: Per H. Hammarlund, Eran Tamari, Lior Zimet, Sergio Kolor, Sergio V. Tota, Sagi Lahav, James Vash, Gaurav Garg, Jonathan M. Redshaw, Steven R. Hutsell, Harshavardhan Kaushikkar, Shawn M. Fukami
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Publication number: 20230058989Abstract: An integrated circuit (IC) including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. For example, the IC may include an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices; and an off-chip interconnect coupled to the interconnect fabric and configured to couple the interconnect fabric to a corresponding interconnect fabric on another instance of the integrated circuit, wherein the interconnect fabric and the off-chip interconnect provide an interface that transparently connects the one or more memory controller circuits, the processor cores, graphics processing units, and peripheral devices in either a single instance of the integrated circuit or two or more instances of the integrated circuit.Type: ApplicationFiled: August 22, 2022Publication date: February 23, 2023Inventors: Per H. Hammarlund, Lior Zimet, Sergio Kolor, Sagi Lahav, James Vash, Gaurav Garg, Tal Kuzi, Jeffry E. Gonion, Charles E. Tucker, Lital Levy-Rubin, Dany Davidov, Steven Fishwick, Nir Leshem, Mark Pilip, Gerard R. Williams, III, Harshavardhan Kaushikkar, Srinivasan Rangan Sridharan