Patents by Inventor Harshit Jaiswal

Harshit Jaiswal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Clock recovery for PAM4 signaling using bin-map
    Patent number: 12218786
    Abstract: A technical solution is directed to a clock recovery apparatus for multi-level signaling on a single-lane communication interface. The apparatus can use bin-map logic to successfully recover a common clock per symbol received on the multi-level signal interface. The multi-level signal can be PAM4 signaling where two bits are encoded to represent four levels. The clock recovery apparatus can detect signal level through individual edge detectors for each of the two bits and can handle jitter up to half-clock period.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: February 4, 2025
    Assignee: Cadence Design Systems, Inc.
    Inventors: Hemlata Bist, Rohit Mishra, Harshit Jaiswal, Shubham Agarwal