Patents by Inventor Harshit Saxena

Harshit Saxena has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12124347
    Abstract: An integrated circuit (IC) includes first and second secure memory elements storing identical data and a memory management system that executes a memory operation on the first secure memory element and a control operation on the second secure memory element simultaneously. The control operation is associated with safety of the IC and is executed to enable error detection in the second secure memory element, fault injection for the second secure memory element, masking of a power profile associated with the memory operation, or a combination thereof. After the execution of the memory operation and the control operation, the memory management system copies the data of the first secure memory element to the second secure memory element to maintain sanity of the second secure memory element.
    Type: Grant
    Filed: January 11, 2023
    Date of Patent: October 22, 2024
    Assignee: NXP B.V.
    Inventors: Neha Srivastava, Gautam Tikoo, Harshit Saxena
  • Publication number: 20240160545
    Abstract: An integrated circuit (IC) includes first and second secure memory elements storing identical data and a memory management system that executes a memory operation on the first secure memory element and a control operation on the second secure memory element simultaneously. The control operation is associated with safety of the IC and is executed to enable error detection in the second secure memory element, fault injection for the second secure memory element, masking of a power profile associated with the memory operation, or a combination thereof. After the execution of the memory operation and the control operation, the memory management system copies the data of the first secure memory element to the second secure memory element to maintain sanity of the second secure memory element.
    Type: Application
    Filed: January 11, 2023
    Publication date: May 16, 2024
    Inventors: Neha Srivastava, Gautam Tikoo, Harshit Saxena