Patents by Inventor HARSHITHA DINESH

HARSHITHA DINESH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250201039
    Abstract: The present invention describes an Artificial Intelligence (AI) based Advanced Driver Assistance System (ADAS) testing tool. The testing tool comprises a processing unit configured to filter out, using a pre-trained noise cancellation ML model, the received audio signals to isolate noise signals from the received audio signals. Sequentially, the processing unit is configured to, using a using a pre-trained audio classification ML model, identify one or more audio signal from the filtered-out audio signals relating to ADAS audio signals and classify each of the one or more identified signals into a frequency class based on their distinct frequency characteristics. Finally, the processing unit is configured to evaluate each of the classified signal based on ADAS actions associated with the vehicle and generate test results of ADAS testing on each of the classified audio signals, based on the evaluation.
    Type: Application
    Filed: August 20, 2024
    Publication date: June 19, 2025
    Inventors: HARSHITHA DINESH, GOKUL ANIL DEEPA, AKASH SHIVANI SHIVASHANKARAIAH, ADITYA LAXMAN RAO, DHANUSH DEVARAHALLI RANGASWAMY, RAMINENI NITHIN KUMAR, TIRUMANYAM SUBRAMANYAM, CHINMAY ROJINDAR
  • Publication number: 20250085349
    Abstract: Disclosed herein is an integrated Hardware-in-the-Loop (HIL) system and a method for testing hardware devices. In an embodiment, system comprises a front panel which may be configured to perform one or more predefined Input/Output (I/O) operations. Further, system comprises a rear panel interfaced with the front panel which may be configured to connect to a Device Under Test (DUT). Furthermore, the system comprises a microcontroller unit configured with an automated test application interface which further comprises a plurality of hardware abstraction layers required for testing hardware devices, wherein the hardware devices may include devices of invariant domain and invariant version.
    Type: Application
    Filed: August 22, 2024
    Publication date: March 13, 2025
    Inventors: AYYAMPERUMAL NARAYANASAMY, HARSHITHA DINESH