Patents by Inventor Harshpreet Singh

Harshpreet Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240429216
    Abstract: An example method includes forming a cavity in a multi-layer substrate of a leadframe. The cavity extends from a first substrate surface of the leadframe into the multi-layer substrate to define a cavity floor spaced from the first substrate surface by a cavity sidewall, and at least one conductive terminal is on the cavity floor. The method also includes placing an inductor module in the cavity, in which the inductor module includes a conductor embedded within a dielectric substrate between spaced apart first and second inductor terminals of the inductor module. The method also includes coupling at least one of the first and second inductor terminals to the at least one conductive terminal on the cavity floor. The method also includes encapsulating the inductor module and at least a portion of the leadframe with a mold compound.
    Type: Application
    Filed: April 30, 2024
    Publication date: December 26, 2024
    Inventors: Jie CHEN, Rajen MURUGAN, Sylvester ANKAMAH-KUSI, Harshpreet Singh Phull BAKSHI, Jonathan NOQUIL
  • Publication number: 20240422661
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may perform, while camped on a cell of a first radio access technology (RAT), a search for closed access group (CAG) cells of a second RAT different from the first RAT. The UE may populate a database based at least in part on the search, wherein populating the database includes associating the cell of the first RAT with one or more of the CAG cells of the second RAT. The UE may perform a reselection process from the cell of the first RAT to a first CAG cell of the second RAT, of the one or more CAG cells of the second RAT. Numerous other aspects are described.
    Type: Application
    Filed: December 17, 2021
    Publication date: December 19, 2024
    Inventors: Xinning SHEN, Osama LOTFALLAH, Qin Xue FRANTTI, Sunitha SUNDARAM, Sivasubramanian RAMALINGAM, Yi REN, Flora Pui San CHAN, Cogol TINA, Jun DENG, Mudita SAIYADH, Harshpreet SINGH
  • Publication number: 20240313404
    Abstract: An electronic device includes a multilevel package substrate, a semiconductor die, and a package structure, the multilevel package substrate has first, second, and third levels including respective dielectric layers and conductive features, the first level including a first trace layer with an antenna and a first via layer with a portion of a ground wall laterally spaced outward from and surrounding the antenna, and the second level including a second trace layer having a ground plane connected to the ground wall, the semiconductor die attached to the first level of the multilevel package substrate, and the package structure including a molding compound enclosing the semiconductor die and extending on a side of the antenna, where the package structure mold compound maters and thickness can be tuned for improved performance.
    Type: Application
    Filed: January 31, 2024
    Publication date: September 19, 2024
    Inventors: Harshpreet Singh Phull Bakshi, Rajen Manicon Murugan, Sylvester Ankamah-Kusi
  • Publication number: 20240213185
    Abstract: An electronic device includes a multilevel package substrate with a horizontal substrate integrated waveguide (SIW) with a channel, a vertical SIW with an opening, a grounded coplanar waveguide (GCPW), a first transition between the horizontal SIW and the GCPW, and a second transition between the horizontal and vertical SIWs, as well as a semiconductor die having conductive structures coupled to a signal trace and a ground trace of the GCPW, and a package structure that encloses the semiconductor die and a portion of the multilevel package substrate.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 27, 2024
    Inventors: Aditya Nitin Jogalekar, Harshpreet Singh Phull Bakshi, Rajen Manicon Murugan, Sylvester Ankamah-Kusi
  • Publication number: 20240071959
    Abstract: In examples, a semiconductor package comprises a conductive terminal; a semiconductor die including a device side having circuitry formed therein, the device side facing toward the conductive terminal; and a substrate coupled to the conductive terminal and to the device side of the semiconductor die. The substrate includes a first metal layer coupled to first and second vias extending toward and coupled to either the device side of the semiconductor die or the conductive terminal. The substrate includes a second metal layer electrically isolated from the first metal layer by an insulation layer between the first and second metal layers, the second metal layer coupled to a third via extending toward and coupled to either the conductive terminal or the semiconductor die. The first and second metal layers form a Marchand balun.
    Type: Application
    Filed: June 30, 2023
    Publication date: February 29, 2024
    Inventors: Harshpreet Singh Phull BAKSHI, Sylvester ANKAMAH-KUSI, Siraj AKHTAR, Rajen Manicon MURUGAN
  • Publication number: 20240021971
    Abstract: An example device includes: a multilayer build-up package substrate including trace conductor layers spaced from one another by dielectric material, and further including connection conductor layers coupling portions of the trace conductor layers through dielectric material, the multilayer build-up package substrate having a device side surface with one of the trace conductor layers and an opposing board side surface with one of the connection conductor layers; and a waveguide transition formed from the multilayer build-up package substrate, the waveguide transition having an input port formed from the connection conductor layer on the board side surface, and having at least two sub-transitions spaced laterally from one another, the at least two sub-transitions to couple a signal from the input port through the trace conductor layers and the connection conductor layers to a coplanar waveguide formed from the trace conductor layer on the device side surface.
    Type: Application
    Filed: July 15, 2023
    Publication date: January 18, 2024
    Inventors: Aditya Nitin Jogalekar, Harshpreet Singh Phull Bakshi, Rajen Murugan, Sylvester Ankamah-Kusi
  • Publication number: 20240021973
    Abstract: In examples, a semiconductor package comprises a semiconductor substrate including a device side having circuitry formed therein. The package also includes a conductive layer positioned above the semiconductor substrate; a patch antenna coupled to the conductive layer and to the device side of the semiconductor substrate; and a mold compound covering the patch antenna. The mold compound has a relative permittivity ranging from 3.4 to 3.5 and a loss tangent ranging from 0.0025 to 0.013.
    Type: Application
    Filed: June 30, 2023
    Publication date: January 18, 2024
    Inventors: Harshpreet Singh Phull BAKSHI, Rajen Manicon MURUGAN, Sylvester ANKAMAH-KUSI
  • Publication number: 20230352850
    Abstract: An example microelectronic device package includes: a multilayer package substrate including a slotted waveguide antenna and having routing conductors, the multilayer package substrate having a device side surface and an opposing board side surface; a semiconductor die mounted to the device side surface of the multilayer package substrate and coupled to slotted waveguide antenna by the routing conductors; and mold compound covering the semiconductor die, and a portion of the multilayer package substrate.
    Type: Application
    Filed: April 28, 2023
    Publication date: November 2, 2023
    Inventors: Yiqi Tang, Rajen Murugan, Harshpreet Singh Phull Bakshi, Sylvester Ankamah-Kusi, Juan Herbsommer, Aditya Nitin Jogalekar
  • Patent number: 11409759
    Abstract: In one general embodiment, a computer-implemented method includes identifying a data dump and a predefined data structure, parsing the predefined data structure to determine one or more identifiers within the predefined data structure, determining that a match exists between one or more elements of the data dump and the one or more determined identifiers of the predefined data structure, and formatting the data dump utilizing the predefined data structure, in response to the determining.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: August 9, 2022
    Assignee: International Business Machines Corporation
    Inventors: Trinh Huy Nguyen, Harshpreet Singh
  • Patent number: 11218881
    Abstract: In various embodiments, a wireless device processor may determine a threat score for a first cell, determine whether the first cell threat score is below a first threat score threshold, update a good neighbor cell data structure using neighbor cell information from the first cell in response to determining that the first cell threat score is below the first threat score threshold, performing cell reselection to a second cell, determine whether the second cell transmits a system information block message indicating fake neighbor cell information, and increase a threat score for the second cell in response to determining that the second cell provides the SIB message indicating fake neighbor cell information and that a good neighbor cell data structure includes an indication of one or more good neighbor cells that are within the time threshold and the location threshold and doing countermeasures in a response to the determination.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: January 4, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Subrato Kumar De, Sivasubramanian Ramalingam, Ankur Bhattacharjee, Rahul Chandrashekar Sahukar, Muralidharan Murugan, Mattias Kaulard Huber, Krishna Ram Budhathoki, Syam Prasad Reddy Battula, Sattwik Nandi, Harshpreet Singh, Gaurav Singh, Rishika Tindola, Arvind Vardarajan Santhanam, Nitin Pant
  • Patent number: 10635573
    Abstract: A method and system including a display; at least one application programming interface (API) including one or more parameters, wherein the API communicates with a code of a system under test; a code testing module including a multiple variant generation and handling module; and a code testing processor in communication with the code testing module and operative to execute processor-executable process steps to cause the system to: receive data identifying the API; display one or more parameters associated with the API; generate, with the multiple variant generation and handling module, one or more variants based on values associated with the one or more parameters; receive the one or more generated variants at a variant injector; inject the one or more generated variants into the code via the API; and execute the code with the one or more injected generated variants. Numerous other aspects are provided.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: April 28, 2020
    Assignee: SAP SE
    Inventors: Vipul Tickoo, Harshpreet Singh, Shweta Goyal
  • Publication number: 20190354465
    Abstract: A method and system including a display; at least one application programming interface (API) including one or more parameters, wherein the API communicates with a code of a system under test; a code testing module including a multiple variant generation and handling module; and a code testing processor in communication with the code testing module and operative to execute processor-executable process steps to cause the system to: receive data identifying the API; display one or more parameters associated with the API; generate, with the multiple variant generation and handling module, one or more variants based on values associated with the one or more parameters; receive the one or more generated variants at a variant injector; inject the one or more generated variants into the code via the API; and execute the code with the one or more injected generated variants. Numerous other aspects are provided.
    Type: Application
    Filed: May 15, 2018
    Publication date: November 21, 2019
    Inventors: Vipul Tickoo, Harshpreet Singh, Shweta Goyal
  • Publication number: 20190155814
    Abstract: In one general embodiment, a computer-implemented method includes identifying a data dump and a predefined data structure, parsing the predefined data structure to determine one or more identifiers within the predefined data structure, determining that a match exists between one or more elements of the data dump and the one or more determined identifiers of the predefined data structure, and formatting the data dump utilizing the predefined data structure, in response to the determining.
    Type: Application
    Filed: January 17, 2019
    Publication date: May 23, 2019
    Inventors: Trinh Huy Nguyen, Harshpreet Singh
  • Patent number: 10242078
    Abstract: In one general embodiment, a computer-implemented method includes identifying a data dump and a predefined data structure, parsing the predefined data structure to determine one or more identifiers within the predefined data structure, determining that a match exists between one or more elements of the data dump and the one or more determined identifiers of the predefined data structure, and formatting the data dump utilizing the predefined data structure, in response to the determining.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Trinh Huy Nguyen, Harshpreet Singh
  • Publication number: 20170277760
    Abstract: In one general embodiment, a computer-implemented method includes identifying a data dump and a predefined data structure, parsing the predefined data structure to determine one or more identifiers within the predefined data structure, determining that a match exists between one or more elements of the data dump and the one or more determined identifiers of the predefined data structure, and formatting the data dump utilizing the predefined data structure, in response to the determining.
    Type: Application
    Filed: March 23, 2016
    Publication date: September 28, 2017
    Inventors: Trinh Huy Nguyen, Harshpreet Singh