Abstract: A branch predictor. A first branch prediction table is coupled to an instruction pointer generator to store tagged branch prediction entries and to provide branch predictions at high speed. A second branch prediction table is also coupled to the instruction pointer generator to store untagged branch prediction entries and to provide branch predictions for a much larger working set of branches, albeit at a slower speed.

Abstract: In one method, a hazard on a register is detected based on the register ID from a latch of a first stage of a processor pipeline. The pipeline is stalled after a stale value of the register is stored in a latch of a later stage of the pipeline. The stale value in the latch is then replaced with a fresh value while the pipeline is stalled.

Abstract: A branch predictor. A first branch prediction table is coupled to an instruction pointer generator to store tagged branch prediction entries and to provide branch predictions at high speed.

Abstract: A microprocessor for efficient processing of instructions in a program flow including a conditional program flow control instruction, such as a branch instruction. The conditional program flow control instruction targets a first code section to be processed if the condition is resolved to be met, and a second code section to be processed if the condition is resolved to be not met. A fetch unit fetches instructions to be processed and branch prediction logic coupled to the fetch unit predicts the resolution of the condition. The branch prediction logic of the invention also determines whether resolution of the condition is unlikely to be predicted accurately. Stream management logic responsive to the branch prediction logic directs speculative processing of instructions from both the first and second code sections prior to resolution of the condition if resolution of the condition is unlikely to be predicted accurately.

Abstract: A system for detecting hazardous conditions during operation of a vehicle. In one embodiment, the system includes a plurality of sensors that monitor a plurality of conditions and transmit condition signals each representing a measure of a condition. A plurality of rate determination circuits is coupled to the sensors and continually receives the condition signals, wherein each rate determination circuit calculates rates of change for the condition, including a baseline rate of change, and outputs a potential hazard value representing a deviation of a rate of change from the baseline rate that exceeds a predetermined threshold value. An evaluation circuit receives the potential hazard value, calculates a new potential hazard value using the potential hazard value and a rate of change for at least one associated condition and determines whether an actual hazard exists by comparing the new potential hazard value with a stored value that corresponds to the condition.

Abstract: A microprocessor for efficient processing of instructions in a program flow including a conditional program flow control instruction, such as a branch instruction. The conditional program flow control instruction targets a first code section to be processed if the condition is resolved to be met, and a second code section to be processed if the condition is resolved to be not met. A fetch unit fetches instructions to be processed and branch prediction logic coupled to the fetch unit predicts the resolution of the condition. The branch prediction logic of the invention also determines whether resolution of the condition is unlikely to be predicted accurately. Stream management logic responsive to the branch prediction logic directs speculative processing of instructions from both the first and second code sections prior to resolution of the condition if resolution of the condition is unlikely to be predicted accurately.

Abstract: A processor microarchitecture for efficient processing of instructions in a program including a program flow control instruction. The program flow control instruction specifies a target instruction and includes one or more candidate instructions between the target instruction and the program flow control instruction. A fetch unit fetches instructions in the program from the memory. Control logic stores one or more candidate instructions in the buffer prior to resolution of the conditional program flow control instruction in response to the fetch unit fetching a program flow control instruction specifying a target instruction within a predetermined number of instructions from the conditional program flow control instruction. In another embodiment, the candidate instructions are stored only if the conditional branch instruction is considered to be difficult to predict.

Abstract: A processor microarchitecture for efficient dynamic instruction scheduling and execution. The invention includes a predetermined number of independent dispatch queues. The invention also includes a cluster of execution units coupled to each dispatch queue such that the dispatch queue and the corresponding cluster of execution units forms an independent micropipeline. Chain-building and steering logic coupled to the dispatch queues identifies a consumer instruction relying on a producer instruction for an operand, and issues the consumer instruction to the same dispatch queue as the producer instruction that it is dependent upon. The instructions are issued from the dispatch queue to the corresponding cluster of execution units. In one embodiment, the output of each execution unit in the cluster is routed to the inputs of all execution units in the cluster such that the result of executing the producer instruction is readily available as an operand for execution of the consumer instruction.

Abstract: A method and apparatus for generating status information about a pipelined processor after the completion of an execution of an instruction. A first storage device stores the current overall status of the processor due to the execution of a plurality of instructions previous to the presently executing instruction. A second storage device stores an instruction status which represents the status of the processor due to the presently executing instruction alone. Logic generates a new overall status which represents the staus of the processor due to the execution of the present instruction and the previous instructions wherein the new overall status is generated from the instruction status and the current overall status.

Abstract: A method and apparatus for executing floating-point instruction pairs in a pipelined manner in which exceptions are predicted during an execution stage. In response to a possible exception, the execution pipeline can stall the pipeline. The floating-point pipeline and the integer pipelines are stalled in an execution stage and a decoding stage, respectively. Once stalled, the floating-point microinstructions are executed, the state of the machine is updated and then any exceptions are reported.

Abstract: A method and apparatus for accessing and manipulating a stack register file during an instruction execution through a pipelined execution unit. A plurality of control directives are provided to the apparatus. A stack register file having a plurality of physical registers is provided for storing data. The physical register file has a stack organization. A pointer table register file having a plurality of pointer table registers stores physical register addresses. A TAG register file comprising a plurality of TAG registers, one for each of the pointer table register, is provided for signalling whether the associated physical register is empty or full. A TOS address generator generates an address of one of the pointer table registers which contains an address of one of the physical registers which is the current top of stack register.

Abstract: A data register file system is provided in a microprocessor having a pipelined execution unit that employs the data register file to store operands and results of its instruction executions. The data register file system includes a plurality of data registers, each of which stores one of the operands and results. A pointer table has a plurality of pointer registers, each storing an address of one of the data registers. A first address generation logic is coupled to the pointer table and the pipelined execution unit for generating a first set of pointer table addresses to access a first group of the pointer registers for the addresses of a first group of the data registers which are required by the execution of a first floating point instruction.