Abstract: A subsystem (200) is provided at least Direct Memory Access (DMA) device (220) utilized to provide instructions to facilitate the operation of a subsystem processor (210). In one embodiment, a system level processor (102) initiates the provision of instructions for a subsystem (210). The DMA device may be additionally or alternatively utilized to provide data transfer capabilities to a plurality of data channels in a subsystem (200). The DMA device processes channels in a time limited manner to ensure that data is processed in a manner appropriate for time critical data.

Abstract: A subsystem (200) is provided at least Direct Memory Access (DMA) device (220) utilized to provide instructions to facilitate the operation of a substem processor (210). In one embodiment, a system level processor (102) initiates the provision of instructions for a subsystem (210). The DMA device may be additionally or alternatively utilized to provide data transfer capabilities to a plurality of data channels in a subsytem (200). The DMA device processes channels in a time limited manner to ensure that data is porcessed in a manner appropriate for time critical data.

Abstract: A frequency rate multiplier to produce an output with an output frequency as a ratio of an input frequency is described. In one embodiment, the frequency rate multiplier includes an accumulator register to store, based upon a first clock signal having the input frequency, a binary representation of the ratio having a first most significant bit and a second most significant bit, a first adder coupled to the accumulator register in a feedback arrangement to receive the binary representation stored in the accumulator register and, based upon the first clock signal, to repeatedly add the accumulator value to a programmable parameter value representing a component of the output frequency to obtain a first result, a secondary adder coupled between the first adder and the accumulator register to receive the first result and, based upon the second most significant bit, to add a constant value to the first result forming a second result to be stored into the accumulator register.

Abstract: An apparatus and method for transferring data within a computer includes a first computer sub-system connected to a second computer sub-system. The first computer sub-system produces data that is passed to the second computer sub-system. The second computer sub-system includes error detection circuitry to identify an original error in the passed data. The original error is identified with a first error identification technique, such as an error correction code technique. The second computer sub-system also includes error perpetuation circuitry to perpetuate an error in the data as it is passed to another computer sub-system. The error perpetuation circuitry perpetuates the error according to a second error identification technique, such as a parity bit error technique. The original data error is thereby perpetuated by converting it to the error identification format used by the computer sub-system to which the data is transferred.

Abstract: A phase detection circuit detects a phase relationship between a first clock signal, characterized by transitions of a given polarity (e.g., rising edges) at a first frequency, and a second clock signal, characterized by transitions of the given polarity at a second frequency that is an integer multiple of the first frequency. Transition indication circuitry generates a transition indication signal responsive to transitions, of the given polarity, of the second clock signal. The transition indication signal includes a transition indication (e.g., a pulse) corresponding to each n.sup.th transition, of the given polarity, of the second clock signal and at a phase that is selectable relative to the first clock signal in response to a transition indication control signal. Sampling circuitry (e.g., one or more latches) samples the transition indication signal responsive to each transition, of the given polarity, of the first clock signal to generate a transition indication sample.