Patents by Inventor Hartej Singh

Hartej Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11829231
    Abstract: A method of generating a core dump in a User Equipment (UE) may include detecting, using at least one processor, a trigger, the trigger including an instruction to generate a core dump of the UE. The method may further include classifying, using the at least one processor, data stored in memory of the UE as Read-Write (RW) data or Read Only (RO) data. The method may further include generating, using the at least one processor, a partial core dump based on the RW data of the memory.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: November 28, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hartej Singh, Mallikarjun Shivappa Bidari, Raju Udava Siddappa, Surajit Pradeep Karmakar, Thejeswara Reddy Pocha, Tushar Vrind, Venkata Raju Indukuri
  • Publication number: 20220171671
    Abstract: A method of generating a core dump in a User Equipment (UE) may include detecting, using at least one processor, a trigger, the trigger including an instruction to generate a core dump of the UE. The method may further include classifying, using the at least one processor, data stored in memory of the UE as Read-Write (RW) data or Read Only (RO) data. The method may further include generating, using the at least one processor, a partial core dump based on the RW data of the memory.
    Type: Application
    Filed: December 1, 2021
    Publication date: June 2, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hartej SINGH, Mallikarjun Shivappa BIDARI, Raju Udava SIDDAPPA, Surajit Pradeep KARMAKAR, Thejeswara Reddy POCHA, Tushar VRIND, Venkata Raju INDUKURI
  • Patent number: 10157160
    Abstract: In one embodiment, a method includes: receiving, via a sideband interface of a multi-root agent associated with a first root space and a second root space, a reset prepare signal to inform the multi-root agent that the first root space is to be reset; sending, via the sideband interface, an acknowledgement signal to acknowledge the reset prepare signal; receiving one or more transactions for the first root space from a fabric coupled to the multi-root agent; and terminating the one or more transactions responsive to the reset prepare signal, where the first root space is in a reset state when the one or more transactions are received. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: December 18, 2018
    Assignee: Intel Corporation
    Inventors: Michael T. Klinglesmith, Mikal C. Hunsaker, William Knolla, Hartej Singh
  • Patent number: 9690353
    Abstract: In an embodiment, a processor includes at least one functional block and a central power controller. The at least one functional block may include at least one block component and block power logic. The block power logic may be to: receive a first request to initiate a first reduced power mode in the at least one functional block, and in response to the first request, send a notification signal to a central power controller. The central power controller may be to, in response to the notification signal: store a first state of the at least one functional block, and initiate the first reduced power mode in the at least one functional block. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: June 27, 2017
    Assignee: Intel Corporation
    Inventors: Douglas Moran, Achmed Rumi Zahir, William Knolla, Hartej Singh, Vasudev Vasu Bibikar, Sanjeev Jahagirdar, Michael Klinglesmith, Irwin Vaz, Varghese George
  • Publication number: 20160357696
    Abstract: In one embodiment, a method includes: receiving, via a sideband interface of a multi-root agent associated with a first root space and a second root space, a reset prepare signal to inform the multi-root agent that the first root space is to be reset; sending, via the sideband interface, an acknowledgement signal to acknowledge the reset prepare signal; receiving one or more transactions for the first root space from a fabric coupled to the multi-root agent; and terminating the one or more transactions responsive to the reset prepare signal, where the first root space is in a reset state when the one or more transactions are received. Other embodiments are described and claimed.
    Type: Application
    Filed: September 25, 2015
    Publication date: December 8, 2016
    Inventors: Michael T. Klinglesmith, Mikal C. Hunsaker, William Knolla, Hartej Singh
  • Publication number: 20140281616
    Abstract: In an embodiment, a processor includes at least one functional block and a central power controller. The at least one functional block may include at least one block component and block power logic. The block power logic may be to: receive a first request to initiate a first reduced power mode in the at least one functional block, and in response to the first request, send a notification signal to a central power controller. The central power controller may be to, in response to the notification signal: store a first state of the at least one functional block, and initiate the first reduced power mode in the at least one functional block. Other embodiments are described and claimed.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Inventors: Douglas Moran, Achmed Rumi Zahir, William Knolla, Hartej Singh, Vasudev Vasu Bibikar, Sanjeev Jahagirdar, Michael Klinglesmith, Irwin Vaz, Varghese George
  • Patent number: 7505407
    Abstract: According to embodiments of the present invention, an adaptable traffic control system, method, article of manufacture, and apparatus receive a user-programmed value representing an amount of target traffic allowed through a connectivity device port and a user-programmed value representing a time interval during which to receive the allowed amount of target traffic. The two values define a percentage of target traffic allowed through the port for a particular port speed. One embodiment determines that port speed changed by a factor of N, scales the time interval by a factor of 1/N, and based on the allowed amount of target traffic and the scaled time interval, drops incoming target traffic when the received percentage of incoming target traffic is equal to (or greater than) the defined percentage of target traffic allowed through the port.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: March 17, 2009
    Assignee: Intel Corporation
    Inventors: Hartej Singh, Muraleedhara H. Navada
  • Publication number: 20060013212
    Abstract: Techniques for receiving a packet at a first packet forwarding device in a stack of packet forwarding devices, providing a port aggregation table having a plurality of entries, wherein at least one entry identifies a plurality of ports associated with at least two packet forwarding devices in the stack, and using the packet and the port aggregation table to select a port of a packet forwarding device in the stack for sending the packet to a device external to the stack.
    Type: Application
    Filed: July 13, 2004
    Publication date: January 19, 2006
    Inventors: Hartej Singh, Muraleedhara Navada, Miguel Guerrero
  • Publication number: 20050220013
    Abstract: According to embodiments of the present invention, an adaptable traffic control system, method, article of manufacture, and apparatus receive a user-programmed value representing an amount of target traffic allowed through a connectivity device port and a user-programmed value representing a time interval during which to receive the allowed amount of target traffic. The two values define a percentage of target traffic allowed through the port for a particular port speed. One embodiment determines that port speed changed by a factor of N, scales the time interval by a factor of 1/N, and based on the allowed amount of target traffic and the scaled time interval, drops incoming target traffic when the received percentage of incoming target traffic is equal to (or greater than) the defined percentage of target traffic allowed through the port.
    Type: Application
    Filed: March 31, 2004
    Publication date: October 6, 2005
    Inventors: Hartej Singh, Muraleedhara Navada