Abstract: The invention relates to a clock generator comprised of a system clock input (2) for applying a high-frequency system clock signal, of a digital input (3) for applying a settable digital increment value, of an adder (6) for adding the increment value with the feedback digital cumulative value of the adder, of an output register (13) for outputting the highest-order data bit of the digital cumulative value as an output clock signal of the clock generator (1) over an output clock line, and of a digital phase deviation calculating unit (30) for calculating the phase deviation of the output clock signal according to the remaining low-order data bits of the digital cumulative value and of the digital increment value, whereby the phase deviation is output as a digital phase deviation value to a digital data output (29).

Abstract: In order to generate a clock signal (fT1) that is coupled to a reference signal (FBAS), especially to an analog video signal, a free-running clock pulse (fT1) is generated from a high-frequency clock pulse (f0) and the reference signal (FBAS) is digitized therewith. In addition, a second clock pulse (fT1) is generated from the high-frequency clock pulse (f0) and the phase deviation between the first clock pulse (fT2) and the second clock pulse (fT1) is determined. The digitized sampling values of the reference signal (FBAS) at the first clock frequency (fT1) are converted, according to the phase deviation determined, into corresponding digitized sampling values having the second clock frequency (fT1) and are used as a target specification for generating the second clock pulse (fT1) thus coupled to the reference signal.

Abstract: In order to generate a clock signal (fT1) that is coupled to a reference signal (FBAS), especially to an analog video signal, a free-running clock pulse (fT1) is generated from a high-frequency clock pulse (f0) and the reference signal (FBAS) is digitized therewith. In addition, a second clock pulse (fT1) is generated from the high-frequency clock pulse (f0) and the phase deviation between the first clock pulse (fT2) and the second clock pulse (fT1) is determined. The digitized sampling values of the reference signal (FBAS) at the first clock frequency (fT1) are converted, according to the phase deviation determined, into corresponding digitized sampling values having the second clock frequency (fT1) and are used as a target specification for generating the second clock pulse (fT1) thus coupled to the reference signal.

Abstract: The invention relates to a clock generator comprised of a system clock input (2) for applying a high-frequency system clock signal, of a digital data input (3) for applying a settable digital increment value, of an adder (6) for adding the increment value with the feedback digital cumulative value of the adder, of an output register (13) for outputting the highest order data bit of the digital cumulative value as an output clock signal of the clock generator (1) over an output clock line, and of a digital phase deviation calculating unit (30) for calculating the phase deviation of the output clock signal according to the remaining low-order data bits of the digital cumulative value and of the digital increment value, whereby the phase deviation is output as a digital phase deviation value to a digital data output (29).

Abstract: A distortion-compensation method for a signal (S) that is transmitted in the blanking intervals of a video signal (CVBS) uses the received signal (S) to determine whether the signal (S) is subject to interference of a specific type. This interference is at least partially compensated for only when a specific limit value is exceeded. A separation stage according to the invention has a measurement apparatus (M) for detecting the presence of the specific type of interference.

Abstract: To synchronize a decoder at the receiving end, particularly an MPEG audio decoder, with the corresponding coder operating at the transmitting end, it is proposed to supply the data decoded by the decoder to a FIFO memory, the output clock rate at which the data are read out or output from the FIFO memory, being adjusted as a function of the loading level of the FIFO memory.