Patents by Inventor Hartmut BUENNING

Hartmut BUENNING has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230230892
    Abstract: A semiconductor device such as a chip-scale package is provided. Aspects of the present disclosure further relate to a method for manufacturing such a device. According to an aspect of the present disclosure, a semiconductor device is provided that includes a conformal coating arranged on its sidewalls and on the perimeter part of the semiconductor die of the semiconductor device. To prevent the conformal coating from covering unwanted areas, such as electrical terminals, a sacrificial layer is arranged prior to arranging the conformal coating. By removing the sacrificial layer, the conformal coating can be removed locally. The conformal coating covers the perimeter part of the semiconductor die by the semiconductor device, in which part a remainder of a sawing line or dicing street is provided.
    Type: Application
    Filed: January 17, 2023
    Publication date: July 20, 2023
    Applicant: NEXPERIA B.V.
    Inventors: Regnerus Hermannus Poelma, Hartmut Bünning, Stefan Berglund, Hans-Juergen Funke, Johannes Josinus Kuipers, Joep Stokkermans, Wolfgang Schnitt
  • Publication number: 20220020679
    Abstract: A semiconductor device is provided that includes a substrate, a pocket within the substrate, a solderable/glueable re-distribution layer arranged in the pocket and a die. The die is arranged downwards, so that a base contact and an emitter contact of the die face the bottom of the device, and a collector contact of the die faces the top of the device. The solderable/glueable re-distribution layer includes a first and second re-distribution layer part and the first re-distribution layer part and the second re-distribution layer part are isolated from each other by an isolating material. The emitter contact is connected to the first re-distribution layer part and the base contact is connected to the second re-distribution layer part. The emitter contacts via the first re-distribution layer part, the base contacts via the second re-distribution layer part, and the collector contact are fan out to the top surface of the semiconductor device.
    Type: Application
    Filed: July 20, 2021
    Publication date: January 20, 2022
    Applicant: NEXPERIA B.V.
    Inventors: Hartmut Bünning, Hans-Juergen Funke, Stefan Berglund, Justin Y.H. Tan, Vegneswary Ramalingam, Roelf Groenhuis, Joep Stokkermans, Thijs Kniknie
  • Publication number: 20220020670
    Abstract: A semiconductor device is provided that includes a frontside and a backside, four sidewalls, a first solder/glue connection on the frontside and a second solder/glue connection on the backside. The semiconductor device is either connected as a chip scale package to a printed circuit board or inside a semiconductor package via one of the four sidewalls, so that the first solder/glue connection and the second solder/glue connection are visible for a visual solder/glue inspection.
    Type: Application
    Filed: July 20, 2021
    Publication date: January 20, 2022
    Applicant: NEXPERIA B.V.
    Inventors: Hartmut Bünning, Hans-Juergen Funke, Stefan Berglund, Justin Y.H. Tan, Vegneswary Ramalingam, Roelf Groenhuis, Joep Stokkermans, Thijs Kniknie
  • Patent number: 11011446
    Abstract: A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, a backside and side surfaces extending between the major surface and the backside. The semiconductor device also includes at least one metal layer extending across the backside of the substrate. A peripheral part of the at least one metal layer located at the edge of the substrate between the backside and at least one of the side surfaces extends towards a plane containing the major surface. This can prevent burrs located at the peripheral part of the at least one metal layer interfering with the mounting of the backside of the substrate on the surface of a carrier.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: May 18, 2021
    Assignee: NEXPERIA B.V.
    Inventors: Tonny Kamphuis, Leo van Gemert, Hans van Rijckevorsel, Sascha Moeller, Hartmut Buenning, Steffen Holland, Y Kuang Huang
  • Patent number: 10410922
    Abstract: A method of manufacturing a device with six-sided protected walls is disclosed. The method includes fabricating the plurality of devices on a wafer, forming a plurality of contact pads on each of the plurality of devices, cutting a first trench around each of the plurality of devices from a backside of the wafer with an active side having a plurality of contact pads facing down, applying a protective coating on the backside of the wafer thus filling the first trench with a protective material of the protective coating on the backside and cutting a second trench from the active side.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: September 10, 2019
    Assignee: NXP B.V.
    Inventor: Hartmut Buenning
  • Patent number: 10347534
    Abstract: Embodiments are provided herein for separating integrated circuit (IC) device die of a wafer, the wafer having a front side with an active device region and a back side, the active device region having a plurality of active devices arranged in rows and columns and separated by cutting lanes, the method including: attaching the front side of the wafer onto a first dicing tape; forming a modification zone within each cutting lane through the back side of the wafer, wherein each modification zone has a first thickness near a corner of each active device and a second thickness near a center point of each active device, wherein the second thickness is less than the first thickness; and propagating cracks through each cutting lane to separate the plurality of active devices.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: July 9, 2019
    Assignee: NXP B.V.
    Inventors: Martin Lapke, Hartmut Buenning, Sascha Moeller, Guido Albermann, Michael Zernack, Leo M. Higgins, III
  • Publication number: 20190080963
    Abstract: Embodiments are provided herein for separating integrated circuit (IC) device die of a wafer, the wafer having a front side with an active device region and a back side, the active device region having a plurality of active devices arranged in rows and columns and separated by cutting lanes, the method including: attaching the front side of the wafer onto a first dicing tape; forming a modification zone within each cutting lane through the back side of the wafer, wherein each modification zone has a first thickness near a corner of each active device and a second thickness near a center point of each active device, wherein the second thickness is less than the first thickness; and propagating cracks through each cutting lane to separate the plurality of active devices.
    Type: Application
    Filed: September 12, 2017
    Publication date: March 14, 2019
    Inventors: Martin LAPKE, Hartmut Buenning, Sascha MOELLER, Guido ALBERMANN, Michael ZERNACK, Leo M. HIGGINS, III
  • Publication number: 20180240707
    Abstract: A method of manufacturing a device with six-sided protected walls is disclosed. The method includes fabricating the plurality of devices on a wafer, forming a plurality of contact pads on each of the plurality of devices, cutting a first trench around each of the plurality of devices from a backside of the wafer with an active side having a plurality of contact pads facing down, applying a protective coating on the backside of the wafer thus filling the first trench with a protective material of the protective coating on the backside and cutting a second trench from the active side.
    Type: Application
    Filed: February 23, 2017
    Publication date: August 23, 2018
    Inventor: Hartmut Buenning
  • Patent number: 9847258
    Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device from a wafer substrate, the wafer substrate having a top-side surface with a plurality of active device die separated by saw lanes and an opposite under-side surface. The method comprises coating the under-side surface of the wafer substrate with a resilient coating, locating the position of the saw lanes from the underside surface, blade dicing trenches in the resilient material to expose under-side bulk material in the position of saw lanes, and plasma etching through the trenches to remove the exposed under-side bulk material.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: December 19, 2017
    Assignee: NXP B.V.
    Inventors: Thomas Rohleder, Hartmut Buenning, Guido Albermann, Sascha Moeller, Martin Lapke
  • Patent number: 9812361
    Abstract: Consistent with an example embodiment, there is a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side. The method comprises pre-grinding the backside of a wafer substrate to a thickness. The front-side of the wafer is mounted onto a protective foil. A laser is applied to the backside of the wafer, at first focus depth to define a secondary modification zone in saw lanes. To the backside of the wafer, a second laser process is applied, at a second focus depth shallower than that of the first focus depth, in the saw lanes to define a main modification zone, the secondary modification defined at a pre-determined location within active device boundaries, the active device boundaries defining an active device area. The backside of the wafer is ground down to a depth so as to remove the main modification zone. The IC device die are separated from one another by stretching the protective foil.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: November 7, 2017
    Assignee: NXP B.V.
    Inventors: Hartmut Buenning, Sascha Moeller, Guido Albermann, Martin Lapke, Thomas Rohleder
  • Publication number: 20170148697
    Abstract: A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, a backside and side surfaces extending between the major surface and the backside. The semiconductor device also includes at least one metal layer extending across the backside of the substrate. A peripheral part of the at least one metal layer located at the edge of the substrate between the backside and at least one of the side surfaces extends towards a plane containing the major surface. This can prevent burrs located at the peripheral part of the at least one metal layer interfering with the mounting of the backside of the substrate on the surface of a carrier.
    Type: Application
    Filed: November 3, 2016
    Publication date: May 25, 2017
    Inventors: Tonny Kamphuis, Leo van Gemert, Hans van Rijckevorsel, Sascha Moeller, Hartmut Buenning, Steffen Holland, Y Kuang Huang
  • Publication number: 20170092540
    Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device from a wafer substrate, the wafer substrate having a top-side surface with a plurality of active device die separated by saw lanes and an opposite under-side surface. The method comprises coating the under-side surface of the wafer substrate with a resilient coating, locating the position of the saw lanes from the underside surface, blade dicing trenches in the resilient material to expose under-side bulk material in the position of saw lanes, and plasma etching through the trenches to remove the exposed under-side bulk material.
    Type: Application
    Filed: September 30, 2015
    Publication date: March 30, 2017
    Inventors: Thomas Rohleder, Hartmut Buenning, Guido Albermann, Sascha Moeller, Martin Lapke
  • Patent number: 9601437
    Abstract: Consistent with an example embodiment, a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side, comprises mounting the front-side of the wafer onto protective foil. A laser is applied to saw lane areas on the backside of the wafer, at a first focus depth to define a modification zone; the modification zone defined at a pre-determined depth within active device boundaries and the active device boundaries defined by the saw lane areas. The protective foil is stretched to separate IC device die from one another and expose active device side-walls. With dry-etching of the active device side-walls, the modification zone is substantially removed.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: March 21, 2017
    Assignee: NXP B.V.
    Inventors: Guido Albermann, Sascha Moeller, Thomas Rohleder, Martin Lapke, Hartmut Buenning
  • Publication number: 20160172243
    Abstract: One example discloses a system for wafer material removal, including: a wafer structures map, identifying a first device structure having a first location and a second device structure having a second location; a material removal controller, coupled to the structures map, and having a material removal beam power level output signal and a material removal beam on/off status output signal; wherein the material removal controller is configured to select a first material removal beam power level and a first material removal beam on/off status corresponding to the first location; and wherein the material removal controller is configured to select a second material removal beam power level and a second material removal beam on/off status corresponding to the second location. Another example discloses an article of manufacture comprises at least one non-transitory, tangible machine readable storage medium containing executable machine instructions for wafer material removal.
    Type: Application
    Filed: December 11, 2014
    Publication date: June 16, 2016
    Inventors: Sascha Moeller, Thomas Rohleder, Guido Albermann, Martin Lapke, Hartmut Buenning
  • Patent number: 9349645
    Abstract: An apparatus, device and method for wafer dicing is disclosed. In one example, the apparatus discloses: a wafer holding device having a first temperature; a die separation bar moveably coupled to the wafer holding device; and a cooling device coupled to the apparatus and having a second temperature which enables the die separation bar to fracture an attachment material in response to movement with respect to the wafer holding device. In another example, the method discloses: receiving a wafer having an attachment material applied to one side of the wafer; placing the wafer in a holding device having a first temperature; urging a die separation bar toward the wafer; and cooling the attachment material to a second temperature, which is lower than the first temperature, until the attachment material fractures in response to the urging.
    Type: Grant
    Filed: October 16, 2013
    Date of Patent: May 24, 2016
    Assignee: NXP B.V.
    Inventors: Martin Lapke, Hartmut Buenning, Sascha Moeller, Guido Albermann, Thomas Rohleder, Heiko Backer
  • Publication number: 20160071770
    Abstract: Consistent with an example embodiment, a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side, comprises mounting the front-side of the wafer onto protective foil. A laser is applied to saw lane areas on the backside of the wafer, at a first focus depth to define a modification zone; the modification zone defined at a pre-determined depth within active device boundaries and the active device boundaries defined by the saw lane areas. The protective foil is stretched to separate IC device die from one another and expose active device side-walls. With dry-etching of the active device side-walls, the modification zone is substantially removed.
    Type: Application
    Filed: September 9, 2014
    Publication date: March 10, 2016
    Inventors: Guido Albermann, Sascha Moeller, Thomas Rohleder, Martin Lapke, Hartmut Buenning
  • Patent number: 9245804
    Abstract: Consistent with an example embodiment, there is a semiconductor device, with an active device having a front-side surface and a backside surface; the semiconductor device of an overall thickness, comprises an active device with circuitry defined on the front-side surface, the front-side surface having an area. The back-side of the active device has recesses f a partial depth of the active device thickness and a width of about the partial depth, the recesses surrounding the active device at vertical edges. There is a protective layer of a thickness on to the backside surface of the active device, the protective material having an area greater than the first area and having a stand-off distance. The vertical edges have the protective layer filling the recesses flush with the vertical edges. A stand-off distance of the protective material is a function of the semiconductor device thickness and the tangent of an angle (?) of tooling impact upon a vertical face the semiconductor device.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: January 26, 2016
    Assignee: NXP B.V.
    Inventors: Christian Zenz, Hartmut Buenning, Leonardus Antonius Elisabeth Van Gemert, Tonny Kamphuis, Sascha Moeller
  • Patent number: 9196537
    Abstract: Consistent with an example embodiment, there is a method for assembling a wafer level chip scale processed (WLCSP) wafer; The wafer has a topside surface and an back-side surface, and a plurality of device die having electrical contacts on the topside surface. The method comprises back-grinding, to a thickness, the back-side surface the wafer. A protective layer of a thickness is molded onto the backside of the wafer. The wafer is mounted onto a sawing foil; along saw lanes of the plurality of device die, the wafer is sawed, the sawing occurring with a blade of a first kerf and to a depth of the thickness of the back-ground wafer. Again, the wafer is sawed along the saw lanes of the plurality of device die, the sawing occurring with a blade of a second kerf, the second kerf narrower than the first kerf, and sawing to a depth of the thickness of the protective layer. The plurality of device die are separated into individual device die.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: November 24, 2015
    Assignee: NXP B.V.
    Inventors: Leonardus Antonius Elisabeth Van Gemert, Hartmut Buenning, Tonny Kamphuis, Sascha Moeller, Christian Zenz
  • Publication number: 20150162306
    Abstract: Consistent with an example embodiment, there is semiconductor device assembled to resist mechanical damage. The semiconductor device comprises an active circuit defined on a top surface, contact areas providing electrical connection to the active circuit. There is a pedestal structure upon which the active circuit is mounted on an opposite bottom surface; the pedestal structure has an area smaller than the area of the active device. An encapsulation, consisting of a molding compound, surrounds the sides and the underside of the active device and it surrounds the contact areas. The encapsulation provides a resilient surface protecting the active device from mechanical damage. A feature of the embodiment is that the contact areas may have solder bumps defined thereon.
    Type: Application
    Filed: February 19, 2015
    Publication date: June 11, 2015
    Inventors: Leonardus Antonius Elisabeth VAN GEMERT, Tonny KAMPHUIS, Hartmut BUENNING, Christian ZENZ
  • Publication number: 20150104931
    Abstract: An apparatus, device and method for wafer dicing is disclosed. In one example, the apparatus discloses: a wafer holding device having a first temperature; a die separation bar moveably coupled to the wafer holding device; and a cooling device coupled to the apparatus and having a second temperature which enables the die separation bar to fracture an attachment material in response to movement with respect to the wafer holding device. In another example, the method discloses: receiving a wafer having an attachment material applied to one side of the wafer; placing the wafer in a holding device having a first temperature; urging a die separation bar toward the wafer; and cooling the attachment material to a second temperature, which is lower than the first temperature, until the attachment material fractures in response to the urging.
    Type: Application
    Filed: October 16, 2013
    Publication date: April 16, 2015
    Applicant: NXP B.V.
    Inventors: Martin Lapke, Hartmut Buenning, Sascha Moeller, Guido Albermann, Thomas Rohleder, Heiko Backer