Abstract: The invention relates to a method for contacting SIPOS-passivated semiconductor zones on a semiconductor body, where the removal of the oxide layer from the wafer surface takes place at the same time as the oxide etching before SIPOS passivation. The double-layered SIPOS passivation consists here of a N-SIPOS layer and a O-SIPOS layer. For contact opening, only the N-SIPOS layer is removed by wet chemical etching. By annealing the previously vaporized and structured metallization, a good contact results which can also carry a high current. The process according to the invention involves a simple sequence of operations and an underetching of the passivation layers and the disadvantages resulting from this are reliably avoided.

Abstract: A planar semiconductor device having a heavily doped channel stopper region of the first conductivity type and at least the following components: a Zener diode having the following regions, seen from an upper surface of the device, an upper diode region of the second conductivity type, a lightly doped first upper component region, of the first conductivity type, in which the upper diode region and the channel stopper region are formed at the upper surface, and a heavily doped lower component region of the first conductivity type; and a component having a second upper component region formed with the upper diode region in the first upper component region at the upper surface and having the same conductivity type as the upper diode region, the first upper component region, the lower component region, and a third upper component region of the first conductivity type and formed in the second upper component region at the upper surface of the device.