Patents by Inventor Hartmut Ruelke

Hartmut Ruelke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050026434
    Abstract: Wafer-to-wafer thickness uniformity may be improved significantly in a process for depositing a silicon nitride layer in that the flow rate of the reactant and the chamber pressure are varied during a deposition cycle. By correspondingly adapting the flow rate and/or the chamber pressure before and after the actual deposition step, the process conditions may be more effectively stabilized, thereby reducing process variations, even after non-deposition phases of the deposition tool, such as a preceding plasma clean process or an idle period of the tool.
    Type: Application
    Filed: June 30, 2004
    Publication date: February 3, 2005
    Inventors: Katja Huy, Hartmut Ruelke, Michael Turner
  • Publication number: 20040214430
    Abstract: The effect of resist poisoning may be eliminated or at least substantially reduced in the formation of a low-k metallization layer, in that a nitrogen-containing barrier layer is provided with a surface modified by plasma treatment. Consequently, diffusion of nitrogen and nitrogen compounds in vias formed in the low-k dielectric layer is significantly suppressed, so that in a subsequent photolithography step interaction of nitrogen and nitrogen compounds with the photoresist is remarkably reduced.
    Type: Application
    Filed: November 19, 2003
    Publication date: October 28, 2004
    Inventors: Hartmut Ruelke, Joerg Hohage, Thomas Werner, Michael Kiene
  • Patent number: 6806191
    Abstract: A copper line that is formed in a patterned dielectric layer has a copper/silicon film formed on a surface thereof to substantially suppress an electromigration path through this surface. In an in situ process, the exposed copper surface is first cleaned by a reactive plasma ambient including nitrogen and ammonia and after a certain clean period, a gaseous compound comprising silicon, for example silane, is added to the reactive plasma ambient to form the copper/silicon film. Additionally, a capping layer may be deposited, wherein due to the copper/silicon film, any deposition technique or even spin-coating may be used.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: October 19, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christian Zistl, Jörg Hohage, Hartmut Rülke, Peter Hübler
  • Patent number: 6797652
    Abstract: The electromigration resistance of Cu lines is significantly improved by depositing a low-k capping layer thereon, e.g., a silicon carbide capping layer having a dielectric constant of about 4.5 to about 5.5. Embodiments include sequentially treating the exposed planarized surface of inlaid Cu with a plasma containing NH3 diluted with N2, discontinuing the plasma and flow of NH3 and N2, pumping out the chamber; introducing trimethylsilane, NH3 and He, initiating PECVD to deposit the silicon carbide capping layer, as at a thickness of about 200 Å to about 800 Å. Embodiments also include Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than about 3.9.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: September 28, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Minh van Ngo, Jeremy I. Martin, Hartmut Ruelke
  • Publication number: 20040152333
    Abstract: A silicon nitride layer having a silicon-rich sub-layer and a standard sub-layer is formed on a copper surface to obtain excellent electromigration characteristics due to the standard sub-layer that is in contact with the copper, while maintaining a superior diffusion barrier behavior due to the silicon-rich sub-layer. By combining these sub-layers, the overall thickness of the silicon nitride layer may be kept small compared to conventional silicon nitride barrier layers, thereby reducing the capacitive coupling of adjacent copper lines.
    Type: Application
    Filed: November 19, 2003
    Publication date: August 5, 2004
    Inventors: Larry Zhao, Jeremy Martin, Hartmut Ruelke
  • Publication number: 20040121621
    Abstract: A method of forming a multi-layer stack over a low-k dielectric layer is disclosed, wherein the multi-layer stack provides an improved anti-reflective effect and an enhanced protection of the underlying low-k dielectric material during the chemical mechanical polishing process. The multi-layer stack comprises silicon dioxide based sub-layers, which may be formed in a highly efficient, non-expensive plasma enhanced deposition method, wherein the optical characteristics may be adjusted by varying a ratio of silane and nitrogen oxide during the deposition.
    Type: Application
    Filed: June 16, 2003
    Publication date: June 24, 2004
    Inventors: Hartmut Ruelke, Joerg Hohage, Thomas Werner, Frank Mauersberger
  • Publication number: 20040121265
    Abstract: During the formation of a metallization layer according to the “via first, trench last” sequence with a low-k dielectric layer, resist poisoning is significantly reduced in that a low-density oxide layer is formed on the low-k dielectric layer, for example by converting an upper portion thereof into an oxide so that prior to and during the formation of the cap layer, out-gassing of volatile materials is enhanced. Since the density of the cap layer is reduced compared to cap layers formed by conventional deposition techniques, out-gassing may still be maintained across the entire substrate surface during the via and trench formation so that a critical level of resist contamination may reliably be avoided.
    Type: Application
    Filed: October 22, 2003
    Publication date: June 24, 2004
    Inventors: Thomas Werner, Hartmut Ruelke, Christof Streck
  • Publication number: 20040084680
    Abstract: The effect of resist poisoning may be eliminated or at least substantially reduced in the formation of a low-k metallization layer, in that a nitrogen-containing barrier/etch stop layer is provided with a significantly reduced nitrogen concentration at an interface in contact with said low-k dielectric material. Consequently, diffusion of nitrogen and nitrogen compounds in vias formed in said low-k dielectric layer is significantly suppressed, so that in a subsequent photolithographic step, interaction of nitrogen and nitrogen compounds with the photoresist is remarkably reduced.
    Type: Application
    Filed: March 31, 2003
    Publication date: May 6, 2004
    Inventors: Hartmut Ruelke, Joerg Hohage, Thomas Werner, Massud Aminpur
  • Patent number: 6720242
    Abstract: A method comprises a “two-step” formation of a front side substrate contact in an FET formed over a buried insulator layer on a substrate, thereby avoiding the difficulties and problems involved in etching openings of high aspect ratio through a stack of different materials, as in a conventional front side substrate contact opening.
    Type: Grant
    Filed: May 3, 2001
    Date of Patent: April 13, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gert Burbach, Frank Heinlein, Johannes Groschopf, Gotthard Jungnickel, Hartmut Ruelke, Carsten Hartig
  • Publication number: 20040041239
    Abstract: A low-k dielectric layer stack is provided including a silicon based dielectric material with a low permittivity, wherein an intermediate silicon oxide based etch indicator layer is arranged at a depth that represents the depth of a trench to be formed in the dielectric layer stack. A thickness of the etch indicator layer is sufficiently small to not unduly compromise the overall permittivity of the dielectric layer stack. On the other hand, the etch indicator layer provides a prominent optical emission spectrum to reliably determine the time point when the etch process has reached the etch indicator layer. Thus, the depth of trenches in highly sophisticated low-k dielectric layer stacks may reliably be adjusted to minimize resistance variations of the metal lines.
    Type: Application
    Filed: April 22, 2003
    Publication date: March 4, 2004
    Inventors: Hartmut Ruelke, Christof Streck, Georg Sulzer
  • Publication number: 20030200984
    Abstract: In a method of cleaning a deposition process chamber, a remotely generated activated gas is supplied to the process chamber, in which, depending on the type of excitation means used, a specified chamber pressure in combination with a two-step clean process allows one to significantly reduce nitrogen fluoride (NF3) consumption and increase throughput.
    Type: Application
    Filed: October 30, 2002
    Publication date: October 30, 2003
    Inventors: Christof Streck, Hartmut Ruelke, Joerg Hohage
  • Patent number: 6599827
    Abstract: The electromigration resistance of capped Cu or Cu alloy interconnects is significantly improved by pumping out the deposition chamber after treating the exposed planarized surface of the Cu or Cu alloy with an ammonia-containing plasma, introducing NH3 and N2 into the deposition chamber, and then ramping up the introduction of SiH4 prior to initiating deposition of a silicon nitride capping layer. Embodiments include ramping up the introduction of SiH4 in two stages prior to initiating plasma enhanced chemical vapor deposition of the silicon nitride capping layer.
    Type: Grant
    Filed: May 2, 2001
    Date of Patent: July 29, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Minh Van Ngo, Steven C. Avanzino, Amit P. Marathe, Hartmut Ruelke
  • Patent number: 6596631
    Abstract: The integrity of the interface and adhesion between a barrier or capping layer and a Cu or Cu alloy interconnect member is significantly enhanced by delaying and/or slowly ramping up the introduction of silane to deposit a silicon nitride capping layer after treating the exposed planarized surface of the Cu or Cu alloy with an ammonia-containing plasma. Other embodiments include purging the reaction chamber with nitrogen at elevated temperature to remove residual gases prior to introducing the wafer for plasma treatment.
    Type: Grant
    Filed: July 26, 2000
    Date of Patent: July 22, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Minh Van Ngo, Hartmut Ruelke, Lothar Mergili, Joerg Hohage, Lu You, Robert A. Huertas, Richard J. Huang
  • Patent number: 6569768
    Abstract: A method for removing discoloration and corrosion of an exposed copper surface and for forming a nitride capping layer on top of the surface provides an in-situ process in which the reactive plasma ambient is constantly maintained during a transition from the surface treatment step to the deposition step for forming the nitride capping layer. Permanently maintained plasma avoids an renewed formation of discoloration on the cleaned copper surface during the transition to the deposition step and at the beginning of the deposition step when silane gas is introduced into the plasma ambient. Moreover, the overall process time is significantly reduced.
    Type: Grant
    Filed: March 12, 2001
    Date of Patent: May 27, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hartmut Ruelke, Joerg Hohage, Minh Van Ngo
  • Publication number: 20030072695
    Abstract: In a method of removing oxidized and discolored portions from a copper surface, a mixture of a reactive gas, such as NH3, and of a purge gas, such as N2, is used with a relatively low high-frequency power to substantially remove all of the copper oxide from the surface. Preferably, a silicon-containing capping layer is subsequently formed on the copper surface, wherein the deposition process can be performed immediately after the surface treatment step without any additional transition step, since the process conditions within the reaction chamber, required for the deposition, are already established.
    Type: Application
    Filed: April 29, 2002
    Publication date: April 17, 2003
    Inventors: Hartmut Ruelke, Joerg Hohage, Minh Van Ngo, Paul Lawrence King, Peter Huebler
  • Patent number: 6506677
    Abstract: The electromigration resistance of capped Cu or Cu alloy interconnects is significantly improved by sequentially and contiguously treating the exposed planarized surface of in-laid Cu with a plasma containing NH3 and N2, ramping up the introduction of SiH4 and then initiating deposition of a silicon nitride capping layer. Embodiments include treating the exposed surface of in-laid Cu with a soft NH3 plasma diluted with N2, ramping up the introduction of SiH4 in two stages, and then initiating plasma enhanced chemical vapor deposition of a silicon nitride capping layer, while maintaining substantially the same pressure, N2 flow rate and NH3 flow rate during plasma treatment, SiH4 ramp up and silicon nitride deposition. Embodiments also include Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than about 3.9.
    Type: Grant
    Filed: May 2, 2001
    Date of Patent: January 14, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Steven C. Avanzino, Minh Van Ngo, Amit P. Marathe, Hartmut Ruelke
  • Publication number: 20020076843
    Abstract: A semiconductor structure is disclosed having a silicon oxynitride ARC layer formed over a material layer to be patterned, wherein the ARC layer comprises a protection layer that prevents contact of the photoresist with nitrogen atoms. The ARC layer is formed by plasma-enhanced chemical vapor deposition so that the optical properties of the ARC layer, such as thickness, refractive index and extinction coefficient, can be precisely controlled.
    Type: Application
    Filed: May 9, 2001
    Publication date: June 20, 2002
    Inventors: Hartmut Ruelke, Martin Mazur, Minh Van Ngo
  • Publication number: 20020072218
    Abstract: A method for removing discoloration and corrosion of an exposed copper surface and for forming a nitride capping layer on top of the surface provides an in-situ process in which the reactive plasma ambient is constantly maintained during a transition from the surface treatment step to the deposition step for forming the nitride capping layer. Permanently maintained plasma avoids an renewed formation of discoloration on the cleaned copper surface during the transition to the deposition step and at the beginning of the deposition step when silane gas is introduced into the plasma ambient. Moreover, the overall process time is significantly reduced compared to a typical prior art process.
    Type: Application
    Filed: March 12, 2001
    Publication date: June 13, 2002
    Inventors: Hartmut Ruelke, Joerg Hohage, Minh Van Ngo
  • Publication number: 20020055244
    Abstract: A method comprises a “two-step” formation of a front side substrate contact in an FET formed over a buried insulator layer on a substrate, thereby avoiding the difficulties and problems involved in etching openings of high aspect ratio through a stack of different materials, as in a conventional front side substrate contact opening.
    Type: Application
    Filed: May 3, 2001
    Publication date: May 9, 2002
    Inventors: Gert Burbach, Frank Heinlein, Johannes Groschopf, Gotthard Jungnickel, Hartmut Ruelke, Carsten Hartig
  • Patent number: 6372668
    Abstract: The present invention is directed to a method of forming process layers comprised of silicon oxynitride. In one embodiment, the method comprises positioning a wafer in a process chamber, introducing silane and nitrous oxide into the chamber at a flow rate ratio ranging from approximately 2.6-3.8 silane to nitrous oxide, and generating a plasma in the chamber using a high frequency to low frequency power setting ratio ranging from approximately 1.2-1.8.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: April 16, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sey-Ping Sun, Homi Nariman, Hartmut Ruelke