Patents by Inventor Hartmut Sturm
Hartmut Sturm has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240077932Abstract: The present disclosure describes a system with a power management device, a wakeup circuit, a battery management device, and a connector. During a powered down mode of operation, the battery management device can provide, via the connector, a bias voltage to the wakeup circuit. In response to a wakeup switch being activated, the battery management device can provide a power supply (e.g., from a battery) to the power management device. Benefits of the wakeup circuit include (1) a reduction of battery consumption—and thus improving battery lifetime—when the electronic system is in a powered down mode of operation because the wakeup circuit has lower number of active components compared to other designs and (2) a non-complex wakeup circuit design because one or more existing connector interconnects between the power management device and the battery management device can be re-used during electronic system's powered down mode of operation.Type: ApplicationFiled: March 16, 2023Publication date: March 7, 2024Applicant: Apple Inc.Inventors: Talbott M. Houk, Wenxun Huang, Nikola Jovanovic, Floyd L. Dankert, Sanjay Pant, Alessandro Molari, Siarhei Meliukh, Nicola Florio, Ludmil N. Nikolov, Nathan F. Hanagami, Hartmut Sturm, Di Zhao, Chad L. Olson, John J. Sullivan, Seyedeh Maryam Mortazavi Zanjani, Tristan R. Hudson, Jay B. Fletcher, Jonathan A. Dutra
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Patent number: 11489533Abstract: An apparatus includes a power converter circuit configured to generate a voltage level on a regulated power supply node using a clock signal, and a clock generation circuit configured to dither a frequency of the clock signal. To transition from a first frequency to a second frequency, the clock generation circuit is configured to change, during an initial transition period, the clock signal between the first and second frequencies such that a particular percentage of clock pulses have the second frequency. During one or more intermediate transition periods, the clock generation circuit is configured to change the clock signal between the first and second frequencies such that a percentage of clock pulses having the second frequency increases relative to a prior transition period. During a final transition period of the series, the clock generation circuit is configured to set the frequency of the clock signal to the second frequency.Type: GrantFiled: April 28, 2020Date of Patent: November 1, 2022Assignee: Apple Inc.Inventors: Bogdan-Eugen Matei, Hartmut Sturm
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Publication number: 20210336626Abstract: An apparatus includes a power converter circuit configured to generate a voltage level on a regulated power supply node using a clock signal, and a clock generation circuit configured to dither a frequency of the clock signal. To transition from a first frequency to a second frequency, the clock generation circuit is configured to change, during an initial transition period, the clock signal between the first and second frequencies such that a particular percentage of clock pulses have the second frequency. During one or more intermediate transition periods, the clock generation circuit is configured to change the clock signal between the first and second frequencies such that a percentage of clock pulses having the second frequency increases relative to a prior transition period. During a final transition period of the series, the clock generation circuit is configured to set the frequency of the clock signal to the second frequency.Type: ApplicationFiled: April 28, 2020Publication date: October 28, 2021Inventors: Bogdan-Eugen Matei, Hartmut Sturm
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Patent number: 9471483Abstract: Electronic apparatus, comprising: non-volatile memory configured to be written to or read from in memory portions which are erased a sector at a time, each said sector comprising a plurality of said portions, and the memory having at least three said sectors each of which is adapted to be erased independently of the others; and control means operable to control erasing of the sectors, wherein: the control means is configured to store in a plurality of the sectors other than a target said sector erasure information concerning an erasure procedure, the erasure procedure involving erasing the target sector, so that such information in the sectors may be inspected to establish a suitable recovery procedure following an interruption event.Type: GrantFiled: July 26, 2011Date of Patent: October 18, 2016Assignee: FUJITSU SEMICONDUCTOR EUROPE GMBHInventors: Richard Landenbach, Marc Willam, Hartmut Sturm, Kai Dieffenbach
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Patent number: 9455587Abstract: A method for charging a battery is provided, wherein current pulses are supplied to the battery, wherein each pulse is followed by a rest period during which no current is supplied to the battery, and wherein the state of charge of the battery is determined during the rest period.Type: GrantFiled: May 27, 2014Date of Patent: September 27, 2016Assignee: Dialog Semiconductor GmbHInventors: Otto Schumacher, Olivier Girard, Joao Paulo Trierveiler Martins, Hartmut Sturm, Fabio Rigoni
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Publication number: 20150102779Abstract: A method for charging a battery is provided, wherein current pulses are supplied to the battery, wherein each pulse is followed by a rest period during which no current is supplied to the battery, and wherein the state of charge of the battery is determined during the rest period.Type: ApplicationFiled: May 27, 2014Publication date: April 16, 2015Applicant: Dialog Semiconductor GmbHInventors: Otto Schumacher, Olivier Girard, Joao Paulo Trierveiler Martins, Hartmut Sturm, Fabio Rigoni
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Publication number: 20130219110Abstract: Electronic apparatus, comprising: non-volatile memory configured to be written to or read from in memory portions which are erased a sector at a time, each said sector comprising a plurality of said portions, and the memory having at least three said sectors each of which is adapted to be erased independently of the others; and control means operable to control erasing of the sectors, wherein: the control means is configured to store in a plurality of the sectors other than a target said sector erasure information concerning an erasure procedure, the erasure procedure involving erasing the target sector, so that such information in the sectors may be inspected to establish a suitable recovery procedure following an interruption event.Type: ApplicationFiled: July 26, 2011Publication date: August 22, 2013Applicant: FUJITSU SEMICONDUCTOR EUROPE GMBHInventors: Richard Landenbach, Marc Willam, Hartmut Sturm, Kai Dieffenbach
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Patent number: 7908308Abstract: A Carry-Select Adder structure comprising a carry generation network and a multiplexer to select a particular pre-calculatad sum of a bit-group via orthogonal signal levels of a Hot-Carry signal provided by said carry generation network (21), wherein in order to provide orthogonal signal levels of said Hot-Carry signal, the carry generation network (21) comprises two carry lookahead trees (22, 23) working in parallel to each other, wherein a first carry lookahead tree (22) provides a first signal level of the Hot-Carry signal, and a second carry lookahead tree (23) provides a second, compared to the first signal level inverse signal level of the Hot-Carry signal. Furthermore a method to operate such a Carry-Select Adder is described.Type: GrantFiled: May 15, 2007Date of Patent: March 15, 2011Assignee: International Business Machines CorporationInventors: Wilhelm Haller, Mark Mayo, Ricardo H. Nigaglioni, Hartmut Sturm
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Publication number: 20080046498Abstract: A Carry-Select Adder structure comprising a carry generation network and a multiplexer to select a particular pre-calculatad sum of a bit-group via orthogonal signal levels of a Hot-Carry signal provided by said carry generation network (21), wherein in order to provide orthogonal signal levels of said Hot-Carry signal, the carry generation network (21) comprises two carry lookahead trees (22, 23) working in parallel to each other, wherein a first carry lookahead tree (22) provides a first signal level of the Hot-Carry signal, and a second carry lookahead tree (23) provides a second, compared to the first signal level inverse signal level of the Hot-Carry signal. Furthermore a method to operate such a Carry-Select Adder is described.Type: ApplicationFiled: May 15, 2007Publication date: February 21, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wilhelm Haller, Mark Mayo, Ricardo H. Nigaglioni, Hartmut Sturm