Patents by Inventor Hartono Darmawaskita

Hartono Darmawaskita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9310828
    Abstract: A complementary output generator (COG) module generates at least two complementary outputs determined by rising and falling event sources. In a simple configuration of the COG module, the rising and falling event sources are the same signal which is a signal having the desired period and duty cycle. The COG module converts this single signal input into dual complementary outputs. The frequency and duty cycle of the dual outputs substantially match those of the single input signal. Blanking and deadband times may be introduced between the complementary outputs, and the dual complementary outputs may also be phase delayed. In addition the COG module may provide up to four outputs for controlling half and full-wave bridge power applications.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: April 12, 2016
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Sean Stacy Steedman, Zeke Lundstrum, Cristian Nicolae Groza, Sebastian Dan Copacian, Hartono DArmawaskita
  • Patent number: 9312844
    Abstract: A slope compensation module provides slope compensation of a switched-mode power supply using current mode control. The slope control unit comprises a capacitor coupled between an input and an output of the slope control unit, a switch for discharging the capacitor and a constant current source for charging the capacitor. Slope compensation parameters may be changed during operation with a programmable constant current source. The slope compensation module may also function as an analog sawtooth waveform frequency generator, and as an analog pulse width modulation (PWM) generator. Charging the capacitor generates a linearly decreasing (negative slope) ramp voltage for modulating a feedback error voltage into a slope compensated feedback error voltage. Capacitor charging may be controlled from a pulse width modulation signal. Opening of the switch may be programmably delayed, and a minimum closed time thereof may also be programmed during operation of the slope compensation module.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: April 12, 2016
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Hartono Darmawaskita, Sean Stacy Steedman, Cristian Nicolae Groza, Marilena Mancioiu, John Robert Charais, Zeke Lundstrum
  • Publication number: 20140132236
    Abstract: A slope compensation module provides slope compensation of a switched-mode power supply using current mode control. The slope control unit comprises a capacitor coupled between an input and an output of the slope control unit, a switch for discharging the capacitor and a constant current source for charging the capacitor. Slope compensation parameters may be changed during operation with a programmable constant current source. The slope compensation module may also function as an analog sawtooth waveform frequency generator, and as an analog pulse width modulation (PWM) generator. Charging the capacitor generates a linearly decreasing (negative slope) ramp voltage for modulating a feedback error voltage into a slope compensated feedback error voltage. Capacitor charging may be controlled from a pulse width modulation signal. Opening of the switch may be programmably delayed, and a minimum closed time thereof may also be programmed during operation of the slope compensation module.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 15, 2014
    Inventors: Hartono Darmawaskita, Sean Stacy Steedman, Cristian Nicolae Groza, Marilena Mancioiu, John Robert Charais, Zeke Lundstrum
  • Publication number: 20140136876
    Abstract: A complementary output generator (COG) module generates at least two complementary outputs determined by rising and falling event sources. In a simple configuration of the COG module, the rising and falling event sources are the same signal which is a signal having the desired period and duty cycle. The COG module converts this single signal input into dual complementary outputs. The frequency and duty cycle of the dual outputs substantially match those of the single input signal. Blanking and deadband times may be introduced between the complementary outputs, and the dual complementary outputs may also be phase delayed. In addition the COG module may provide up to four outputs for controlling half and full-wave bridge power applications.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 15, 2014
    Inventors: Sean Stacy Steedman, Zeke Lundstrum, Cristian Nicolae Groza, Sebastian Dan Copacian, Hartono DArmawaskita
  • Patent number: 8487685
    Abstract: An enhanced complementary waveform generator (ECWG) generates two complementary pulse width modulation (PWM) outputs determined by rising and falling event sources. In a simple configuration of the ECWG, the rising and falling event sources are the same signal which is a PWM signal having the desired period and duty cycle. The ECWG converts this single PWM input into dual complementary PWM outputs. The frequency and duty cycle of the dual PWM outputs substantially match those of the single input PWM signal. Blanking and deadband times may be introduced between the dual complementary PWM outputs, and the dual complementary PWM outputs may also be phase delayed.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: July 16, 2013
    Assignee: Microchip Technology Incorporated
    Inventors: Sean Steedman, Hartono Darmawaskita, Stephen Bowling, Cristian Groza, Ward Brown, Zacharias Martin Smit
  • Publication number: 20130057330
    Abstract: An enhanced complementary waveform generator (ECWG) generates two complementary pulse width modulation (PWM) outputs determined by rising and falling event sources. In a simple configuration of the ECWG, the rising and falling event sources are the same signal which is a PWM signal having the desired period and duty cycle. The ECWG converts this single PWM input into dual complementary PWM outputs. The frequency and duty cycle of the dual PWM outputs substantially match those of the single input PWM signal. Blanking and deadband times may be introduced between the dual complementary PWM outputs, and the dual complementary PWM outputs may also be phase delayed.
    Type: Application
    Filed: March 30, 2012
    Publication date: March 7, 2013
    Inventors: Sean Steedman, Hartono Darmawaskita, Stephen Bowling, Cristian Groza, Ward Brown, Zacharias Martin Smit
  • Patent number: 7644217
    Abstract: A low power Universal Serial Bus (USB) capable device uses a weak pull-up resistance that is coupled to at least one data line of the USB for detection of when the USB capable device is connected to a USB host or hub. When the USB capable device is not connected to the USB host or hub, USB peripheral, including the USB transceiver, USB voltage regulator, serial interface and/or USB logic circuits required for USB operation may be powered down to conserve power drawn by the USB capable device. When the USB capable device is connected to the USB host or hub, a voltage from the weak pull-up will be significantly reduced, thus signaling that the USB peripheral and associated circuits should be powered up for normal USB operation.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: January 5, 2010
    Assignee: Microchip Technology Incorporated
    Inventors: Daniel Butler, Hartono Darmawaskita
  • Publication number: 20080215765
    Abstract: A low power Universal Serial Bus (USB) capable device uses a weak pull-up resistance that is coupled to at least one data line of the USB for detection of when the USB capable device is connected to a USB host or hub. When the USB capable device is not connected to the USB host or hub, USB peripheral, including the USB transceiver, USB voltage regulator, serial interface and/or USB logic circuits required for USB operation may be powered down to conserve power drawn by the USB capable device. When the USB capable device is connected to the USB host or hub, a voltage from the weak pull-up will be significantly reduced, thus signaling that the USB peripheral and associated circuits should be powered up for normal USB operation.
    Type: Application
    Filed: March 2, 2007
    Publication date: September 4, 2008
    Inventors: Daniel Butler, Hartono Darmawaskita
  • Patent number: 7231533
    Abstract: A wake-up reset circuit is provided that generates a reset signal to a digital circuit upon a wake-up event. The wake-up reset circuit places the digital circuit into a known reset condition upon wake-up, even if a brown out condition occurs which may have caused unstable and unknown logic states in sequential circuit elements, e.g., volatile memory, flip flops and/or latching circuits. The wake-up reset circuit draws substantially no current when not generating the reset signal.
    Type: Grant
    Filed: August 24, 2004
    Date of Patent: June 12, 2007
    Assignee: Microchip Technology Incorporated
    Inventors: Hartono Darmawaskita, Layton Eagar, Ryan Scott Ellison, Vivien Delport
  • Publication number: 20050138454
    Abstract: A wake-up reset circuit is provided that generates a reset signal to a digital circuit upon a wake-up event. The wake-up reset circuit places the digital circuit into a known reset condition upon wake-up, even if a brown out condition occurs which may have caused unstable and unknown logic states in sequential circuit elements, e.g., volatile memory, flip flops and/or latching circuits. The wake-up reset circuit draws substantially no current when not generating the reset signal.
    Type: Application
    Filed: August 24, 2004
    Publication date: June 23, 2005
    Inventors: Hartono Darmawaskita, Layton Eagar, Ryan Ellison, Vivien Delport
  • Publication number: 20040225766
    Abstract: The present invention relates generally to functional pathway configurations at the interfaces between integrated circuits (ICs) and the circuit assemblies with which the ICs communicate. More particularly, the present invention relates generally to the functional pathway configuration at the interface between a semiconductor chip including an IC (e.g., computer chips like microcontrollers and microprocessors) and the circuitry of a system including the chip. Even more particularly, the present invention relates to a 20-pin microcontroller functional pathway configuration for the interface between the microcontroller and a system in which the microcontroller is embedded.
    Type: Application
    Filed: January 25, 2001
    Publication date: November 11, 2004
    Inventors: Ryan Scott Ellison, Hartono Darmawaskita
  • Patent number: 6542106
    Abstract: A comparator is used as a microcontroller peripheral and is programmable for either high-speed or low-power operation. High-speed operation requires higher operating current than the operating current required in the low-power mode, but enables much faster response to changes in input signals. When in the low-power mode, the quiescent current of the comparator circuit is minimal but the response is slower to changing input signals. Current control is used on the first input stage, which affects the current consumption of the subsequent stages. The current consumption is adjusted by switching in and out different current sources for the differential input stage of the comparator.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: April 1, 2003
    Assignee: Microchip Technology Incorporated
    Inventors: Hartono Darmawaskita, Miguel Moreno
  • Patent number: 6535061
    Abstract: A configurable operational amplifier which is programmed to specific characteristics and parameters for various requirements in the measurement of analog signals. These programmable characteristics and parameters are gain bandwidth product (GBWP), selection of operational amplifier (op-amp) or comparator modes of operation, input offset zero calibration, ultra low input bias current, rail-to-rail input operation, and rail-to-rail output operation. The configurable operational amplifier is used in combination with a microcontroller system, and may be fabricated on an integrated circuit die or in a multi-chip package.
    Type: Grant
    Filed: December 6, 2000
    Date of Patent: March 18, 2003
    Assignee: Microchip Technology Incorporated
    Inventors: Hartono Darmawaskita, Layton Eagar
  • Patent number: 6515464
    Abstract: Input offset voltage calibration of an analog device, or plurality of analog devices, is controlled by a microcontroller. The microcontroller and analog device(s) are fabricated on an integrated circuit die or in a multi-chip package. The microcontroller applies a digital word to an input offset voltage compensation circuit of the analog device for generating input offset voltage compensation. The analog device is switched to a calibrate mode and a voltage comparator compares the output of the analog input device and a voltage reference. When the output of the analog input device is equal to or greater than the voltage reference, the comparator output signals the microcontroller by changing its output logic level. The input offset voltage compensation circuit of the analog input device has a storage register or memory that retains the digital word which compensates for the input offset voltage.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: February 4, 2003
    Assignee: Microchip Technology Incorporated
    Inventors: Hartono Darmawaskita, Layton Eagar, Miguel Moreno
  • Patent number: 6459335
    Abstract: An auto-calibration circuit minimizes input offset voltage in an integrated circuit analog input device. The auto-calibration circuit may also calibrate a plurality of analog input devices on an integrated circuit die or in a multi-chip package (MCP). The auto-calibration circuit and analog input device(s) may be fabricated in combination with a microcontroller system on an integrated circuit die or in an MCP. The auto-calibration circuit controls input offset voltage compensation circuit that counteracts or compensates for input offset voltage so as to minimize voltage error at the output of the analog input device. A digital control circuit applies a digital word to the input offset voltage compensation circuit for generating the required input offset voltage compensation. A linear search or binary search of various values of the digital word may be used by the digital control circuit.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: October 1, 2002
    Assignee: Microchip Technology Incorporated
    Inventors: Hartono Darmawaskita, Layton Eagar, Miguel Moreno
  • Patent number: 6456044
    Abstract: A single integrated circuit package for controlling the charging circuits of a battery charger. The single integrated circuit package comprises a microcontroller, switch mode power supply controller(s), analog to digital converter and analog input multiplexer which may be fabricated on a single integrated circuit die, or the microcontroller may be on one integrated circuit die, and the remaining aforementioned circuits may be on a second integrated circuit die. The switch mode power supply controller is adapted for connection to a power converter which is used to control the voltage and/or current to a battery being charged. The power converter may also be on the same integrated circuit die as the switch mode power supply controller, or may be on a separate semiconductor die but included in the single integrated circuit package. Single or multiple batteries may be charged using charging algorithms specifically tailored to each battery.
    Type: Grant
    Filed: January 31, 2001
    Date of Patent: September 24, 2002
    Assignee: Microchip Technology Incorported
    Inventor: Hartono Darmawaskita
  • Publication number: 20020067206
    Abstract: A configurable operational amplifier which is programmed to specific characteristics and parameters for various requirements in the measurement of analog signals. These programmable characteristics and parameters are gain bandwidth product (GBWP), selection of operational amplifier (op-amp) or comparator modes of operation, input offset zero calibration, ultra low input bias current, rail-to-rail input operation, and rail-to-rail output operation. The configurable operational amplifier is used in combination with a microcontroller system, and may be fabricated on an integrated circuit die or in a multi-chip package.
    Type: Application
    Filed: December 6, 2000
    Publication date: June 6, 2002
    Inventors: Hartono Darmawaskita, Layton Eagar
  • Patent number: 6184659
    Abstract: A single integrated circuit package for controlling the charging circuits of a battery charger. The single integrated circuit package comprises a microcontroller, switch mode power supply controller(s), analog to digital converter and analog input multiplexer which may be fabricated on a single integrated circuit die, or the microcontroller may be on one integrated circuit die, and the remaining aforementioned circuits may be on a second integrated circuit die. The switch mode power supply controller is adapted for connection to a power converter which is used to control the voltage and/or current to a battery being charged. The power converter may also be on the same integrated circuit die as the switch mode power supply controller, or may be on a separate semiconductor die but included in the single integrated circuit package. Single or multiple batteries may be charged using charging algorithms specifically tailored to each battery.
    Type: Grant
    Filed: February 16, 1999
    Date of Patent: February 6, 2001
    Assignee: Microchip Technology Incorporated
    Inventor: Hartono Darmawaskita
  • Patent number: 6078208
    Abstract: A precision temperature sensor produces a clock frequency which varies predictably over wide variations of ambient temperature. The invention has a oscillation generator, two independent current generators, a reference oscillator and a frequency counter. The outputs of the two independent current generators are combined to provide an approximately linear capacitor charging current which is directly proportional to changes in temperature. The capacitor charging current is used to drive the oscillation generator which outputs a clock frequency that is approximately linearly dependent on temperature with determinable slope and intercept. The frequency counter compares the output of the oscillation generator with the independent reference oscillator to compute a digital value for temperature. The precision temperature sensor is implemented on a single, monolithic integrated circuit.
    Type: Grant
    Filed: May 28, 1998
    Date of Patent: June 20, 2000
    Assignee: Microchip Technology Incorporated
    Inventors: James B. Nolan, Hartono Darmawaskita
  • Patent number: 6020792
    Abstract: A precision relaxation oscillator with temperature compensation produces a stable clock frequency over wide variations of ambient temperature. The invention has a oscillation generator and two independent current generators. The outputs of the two programmable, independent current generators are combined to provide a capacitor charging current which is independent of temperature. The precision relaxation oscillator with temperature compensation is implemented on a single, monolithic integrated circuit.
    Type: Grant
    Filed: March 19, 1998
    Date of Patent: February 1, 2000
    Assignee: Microchip Technology Inc.
    Inventors: James B. Nolan, Hartono Darmawaskita, R. Scott Ellison, David Susak