Abstract: A processor is provided with an interrupt capture and hold mechanism. In one embodiment, a processor includes an instruction pipeline having stages for executing instructions. In the event of an exception, the instructions in the pipeline are flushed or aborted. This requires that each stage in the pipeline receive and respond to an exception-causing signal. An interrupt is an exception causing signal which may be provided by circuitry external to the processor. To ensure that such a signal is asserted long enough for each stage in the pipeline to receive and respond to it, all external hardware interrupts are routed through an interrupt capture and hold mechanism, thereby advantageously preventing the causation of an undefined processor state with little added complexity.

Abstract: A processor is provided which performs relative addressing using the exception program counter. In one embodiment, a pipelined processor is provided with an exception program counter (EPC) register chain for tracking exception re-entry points in the instruction stream, and the instruction pipeline is provided with access to at least one of the registers in the register chain. The pipeline includes a fetch stage, a decode stage, and an execute stage. The exception PC register is identified by the decode stage as an operand in a memory access instruction for the execute stage to operate on. The execute stage then adds the contents of the exception PC register to the contents of a processor register or to a literal value to determine a target memory address.