Abstract: One embodiment relates to a method of performing a latency measurement within an integrated circuit. Receipt of a word that contains a beginning of a frame is detected by a frame begin detect circuit in a decoding circuit block. A begin frame detected signal is fed back to the physical media attachment circuit, and an asynchronous signal from the physical media attachment circuit is transmitted at a beginning of a subsequent frame to a time measurement circuit in a core of the integrated circuit. A bitcount may be used to generate a synchronous signal that is also transmitted to the core. At the core of the integrated circuit, a first time is measured that corresponds to receipt of the asynchronous signal and a second time is measured that corresponds to receipt of the synchronous signal. A latency is determined at least by subtracting the first time subtracted from the second time. Other embodiments and features are also disclosed.

Abstract: A novel and efficient method is described that creates a monolithic high capacity Packet Engine (PE) by connecting N lower capacity Packet Engines (PEs) via a novel Chip-to-Chip (C2C) interface. The C2C interface is used to perform functions, such as memory bit slicing and to communicate shared information, and enqueue/dequeue operations between individual PEs.

Abstract: A novel and efficient method is described that creates a monolithic high capacity Packet Engine (PE) by connecting N lower capacity Packet Engines (PEs) via a novel Chip-to-Chip (C2C) interface. The C2C interface is used to perform functions, such as memory bit slicing and to communicate shared information, and enqueue/dequeue operations between individual PEs.

Abstract: A novel and efficient method is described that creates a monolithic high capacity Packet Engine (PE) by connecting N lower capacity Packet Engines (PEs) via a novel Chip-to-Chip (C2C) interface. The C2C interface is used to perform functions, such as memory bit slicing and to communicate shared information, and enqueue/dequeue operations between individual PEs.

Abstract: A novel and efficient method is described that creates a monolithic high capacity Packet Engine (PE) by connecting N lower capacity Packet Engines (PEs) via a novel Chip-to-Chip (C2C) interface. The C2C interface is used to perform functions, such as memory bit slicing and to communicate shared information, and enqueue/dequeue operations between individual PEs.

Abstract: A novel and efficient method is described that creates a monolithic high capacity Packet Engine (PE) by connecting N lower capacity Packet Engines (PEs) via a novel Chip-to-Chip (C2C) interface. The C2C interface is used to perform functions, such as memory bit slicing and to communicate shared information, and enqueue/dequeue operations between individual PEs.

Abstract: A novel hashing function and hashing collision resolution method are introduced that combine multiple known hashing resolution methods to achieve a very low collision probability that is specifically useful in lookup of long keys, such as (for example) the VLAN and MAC lookup in Ethernet switches. However, the system and method introduced here can be used in any networking and telecommunication systems.

Abstract: A novel and efficient method is described that creates a monolithic high capacity Packet Engine (PE) by connecting N lower capacity Packet Engines (PEs) via a novel Chip-to-Chip (C2C) interface. The C2C interface is used to perform functions, such as memory bit slicing and to communicate shared information, and enqueue/dequeue operations between individual PEs.

Abstract: A novel hashing function and hashing collision resolution method are introduced that combine multiple known hashing resolution methods to achieve a very low collision probability that is specifically useful in lookup of long keys, such as (for example) the VLAN and MAC lookup in Ethernet switches. However, the system and method introduced here can be used in any networking and telecommunication systems.

Abstract: A method and apparatus provide means for saving and restoring processor register values and allocating and deallocating stack memory. A first field of a save instruction encodes whether a value in a register of a processor is saved as an argument value or a static value. A second field of the save instruction encodes a size of a stack frame created during execution of the save instruction. An argument value is saved in a calling program's stack frame. A static value is saved in a called program's stack frame. A restore instruction is used to restore static values and deallocate the stack frame. The save and restore instructions may be executed using any programmable device, including a single instruction set architecture processor or a multi-instruction set architecture processor.

Abstract: A multiply unit includes support for arithmetic operations, binary polynomial operations, and permutations.

Abstract: A method and apparatus provide means for saving and restoring processor register values and allocating and deallocating stack memory. A first field of a save instruction encodes whether a value in a register of a processor is saved as an argument value or a static value. A second field of the save instruction encodes a size of a stack frame created during execution of the save instruction. An argument value is saved in a calling program's stack frame. A static value is saved in a called program's stack frame. A restore instruction is used to restore static values and deallocate the stack frame. The save and restore instructions may be executed using any programmable device, including a single instruction set architecture processor or a multi-instruction set architecture processor.

Abstract: A microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The compressed instruction set is a variable length instruction set including 16-bit and 32-bit instructions. The 32-bit instructions are coded using an extend opcode, which indicates that the instruction being fetched is an extended (e.g. 32 bit) instruction. The compressed instruction set further includes multiple sets of register mappings from the compressed register fields to the decompressed register fields. Certain select instructions are assigned two opcode encodings, one for each of two mappings of the corresponding register fields. The compressed register field is directly copied into a portion of the decompressed register field while the remaining portion of the decompressed register field is created using a small number of logic gates.

Abstract: A microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The compressed instruction set is a variable length instruction set including 16-bit and 32-bit instructions. The 32-bit instructions are coded using an extend opcode, which indicates that the instruction being fetched is an extended (e.g. 32 bit) instruction. The compressed instruction set further includes multiple sets of register mappings from the compressed register fields to the decompressed register fields. Certain select instructions are assigned two opcode encodings, one for each of two mappings of the corresponding register fields. The compressed register field is directly copied into a portion of the decompressed register field while the remaining portion of the decompressed register field is created using a small number of logic gates.

Abstract: A microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The compressed instruction set is a variable length instruction set including 16-bit and 32-bit instructions. The 32-bit instructions are coded using an extend opcode, which indicates that the instruction being fetched is an extended (e.g. 32 bit) instruction. The compressed instruction set further includes multiple sets of register mappings from the compressed register fields to the decompressed register fields. Certain select instructions are assigned two opcode encodings, one for each of two mappings of the corresponding register fields. The compressed register field is directly copied into a portion of the decompressed register field while the remaining portion of the decompressed register field is created using a small number of logic gates.

Abstract: A circuit and method is provided which allows a microprocessor to implement speculative load instructions with implicit exception checking. In one embodiment of the method, exception information is generated in response to a memory access exception caused by a speculative load instruction for loading one of a plurality of first registers with data from memory. The exception information, once generated, is stored within one of a plurality of second registers. Each of the second registers corresponds to at least one of the plurality of first registers and is configured to store exception information. Thereafter, an instruction for operating on data stored in a first register is received and decoded by the microprocessor. In response, a second register corresponding to the first register is accessed. If this second register contains exception information, then the microprocessor initiates the exception routine.

Abstract: A circuit and method is provided which allows a microprocessor to implement speculative load instructions with implicit exception checking. In one embodiment of the method, exception information is generated in response to a memory access exception caused by a speculative load instruction for loading one of a plurality of first registers with data from memory. The exception information, once generated, is stored within one of a plurality of second registers. Each of the second registers corresponds to at least one of the plurality of first registers and is configured to store exception information. Thereafter, an instruction for operating on data stored in a first register is received and decoded by the microprocessor. In response, a second register corresponding to the first register is accessed. If this second register contains exception information, then the microprocessor initiates the exception routine.

Abstract: A circuit and method is provided for initiating an exception routine using exception information stored within architectured registers. Exception information is generated in response to a memory access exception caused by a speculative load instruction for loading a first register data from memory. The exception information, once generated, is stored within a first register. Thereafter, an instruction for operating on data stored in a second register is received and decoded. In response, the second register is checked to determine whether the second register contained exception information. If the second register contains exception information, then an exception routine is initiated. If, however, a second register does not contain exception information, then the instruction is executed and data within the second register is used in the execution.

Abstract: A write-through data cache which incorporates a line addressable locking mechanism. By executing a software lock instruction or unlock instruction, a microprocessor controls the locking or unlocking of individual cache lines in the data cache. A locked cache line is not subject to deallocation. By locking a plurality of lines in the data cache, the microprocessor configures a reserved area of guaranteed fast access memory within the data cache. The data cache includes a mechanism to disable write-through of write requests on a line addressable basis. By executing a software write-through disable instruction, the microprocessor commands the data cache to disable write through operations on an individual cache line. By disabling write-through on cache lines which have been locked, the plurality of locked lines behaves like a true fast-access internal memory with guaranteed access time: write requests targeting the reserved area of locked lines are not written through to the bus interface.

Abstract: A microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The compressed instruction set is a variable length instruction set including 16-bit and 32-bit instructions. The 32-bit instructions are coded using an extend opcode, which indicates that the instruction being fetched is an extended (e.g. 32 bit) instruction. The compressed instruction set further includes multiple sets of register mappings from the compressed register fields to the decompressed register fields. Certain select instructions are assigned two opcode encodings, one for each of two mappings of the corresponding register fields. The decompression of the immediate field used for load/store instructions having the global pointer register as a base register is optimized for mixed compressed/non-compressed instruction execution. The immediate field is decompressed into a decompressed immediate field for which the most significant bit is set.