Patents by Inventor Harufumi Kobayashi
Harufumi Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8500984Abstract: A method for manufacturing a printed circuit board having an insulative board and a plurality of electroconductive pads arranged in a grid shape on the insulative board, the method including a step for forming an electroconductive film on the insulative board; a step for forming a pattern on the electroconductive film so as to form the electroconductive pads, a lead wire connected to at least one of the electroconductive pads, and inter-pad wiring for electrically connecting each of the electroconductive pads not connected to the lead wire to any of the electroconductive pads connected to the lead wire, the inter-pad wiring being disposed between mutually adjacent electroconductive pads; a step for plating each of the electroconductive pads by immersing the insulative board in a plating bath and energizing each of the electroconductive pads through the lead wire; and a step for removing the inter-pad wiring.Type: GrantFiled: June 24, 2009Date of Patent: August 6, 2013Assignee: Oki Semiconductor Co., Ltd.Inventors: Yoshimi Egawa, Harufumi Kobayashi
-
Patent number: 8501542Abstract: A dual-face package has an LSI chip sealed with a mold resin, and electrodes for external connections on both of the front face and the back face. The LSI chip is bonded onto the die pad of a leadframe whose outer lead portions are exposed as back-face electrodes at at least the back face. The LSI chip and a plurality of inner lead portions of the leadframe are connected by wiring. At least some of the plurality of inner lead portions have front-face electrodes integrally formed by working a portion of the leadframe. Head faces of the front-face electrodes, or bump electrodes connected to the respective head faces of the front-face electrodes serve as electrodes for external connections to another substrate, element, or the like.Type: GrantFiled: March 5, 2012Date of Patent: August 6, 2013Assignee: Oki Semiconductor Co., LtdInventors: Masamichi Ishihara, Harufumi Kobayashi
-
Publication number: 20120164790Abstract: A dual-face package has an LSI chip sealed with a mold resin, and electrodes for external connections on both of the front face and the back face. The LSI chip is bonded onto the die pad of a leadframe whose outer lead portions are exposed as back-face electrodes at at least the back face. The LSI chip and a plurality of inner lead portions of the leadframe are connected by wiring. At least some of the plurality of inner lead portions have front-face electrodes integrally formed by working a portion of the leadframe. Head faces of the front-face electrodes, or bump electrodes connected to the respective head faces of the front-face electrodes serve as electrodes for external connections to another substrate, element, or the like.Type: ApplicationFiled: March 5, 2012Publication date: June 28, 2012Inventors: Masamichi Ishihara, Harufumi Kobayashi
-
Patent number: 8154110Abstract: A dual-face package has an LSI chip sealed with a mold resin, and electrodes for external connections on both of the front face and the back face. The LSI chip is bonded onto the die pad of a leadframe whose outer lead portions are exposed as back-face electrodes at least the back face. The LSI chip and a plurality of inner lead portions of the leadframe are connected by wiring. At least some of the plurality of inner lead portions have front-face electrodes integrally formed by working a portion of the leadframe. Head faces of the front-face electrodes, or bump electrodes connected to the respective head faces of the front-face electrodes serve as electrodes for external connections to another substrate, element, or the like.Type: GrantFiled: November 2, 2006Date of Patent: April 10, 2012Assignee: Oki Semiconductor Co., LtdInventors: Masamichi Ishihara, Harufumi Kobayashi
-
Publication number: 20090321266Abstract: There is provided a method for manufacturing a printed circuit board having an insulative board and a plurality of electroconductive pads arranged in a grid shape on the insulative board, the method comprising: a step for forming an electroconductive film on the insulative board; a step for forming a pattern on the electroconductive film so as to form the electroconductive pads, a lead wire connected to at least one of the electroconductive pads, and inter-pad wiring for electrically connecting each of the electroconductive pads not connected to the lead wire to any of the electroconductive pads connected to the lead wire, the inter-pad wiring being disposed between mutually adjacent electroconductive pads; a step for plating each of the electroconductive pads by immersing the insulative board in a plating bath and energizing each of the electroconductive pads through the lead wire; and a step for removing the inter-pad wiring.Type: ApplicationFiled: June 24, 2009Publication date: December 31, 2009Applicant: OKI SEMICONDUCTOR CO., LTD.Inventors: Yoshimi Egawa, Harufumi Kobayashi
-
Publication number: 20090224381Abstract: A dual-face package has an LSI chip sealed with a mold resin, and electrodes for external connections on both of the front face and the back face. The LSI chip is bonded onto the die pad of a leadframe whose outer lead portions are exposed as back-face electrodes at least the back face. The LSI chip and a plurality of inner lead portions of the leadframe are connected by wiring. At least some of the plurality of inner lead portions have front-face electrodes integrally formed by working a portion of the leadframe. Head faces of the front-face electrodes, or bump electrodes connected to the respective head faces of the front-face electrodes serve as electrodes for external connections to another substrate, element, or the like.Type: ApplicationFiled: November 2, 2006Publication date: September 10, 2009Inventors: Masamichi Ishihara, Harufumi Kobayashi
-
Patent number: 6852564Abstract: A semiconductor device is disclosed which includes a semiconductor chip having a plurality of electrode pads on its upper surface; terminals such as copper posts formed on the upper surface of the semiconductor chip, and electrically connected to each of the electrode pads; a resin deposited on the upper surface of the semiconductor chip, encapsulating the terminals but exposing at least some of them to a predetermined height; and electroconductor members such as solder balls connected to the terminals. There is also disclosed a method of fabricating such a semiconductor device.Type: GrantFiled: November 27, 2002Date of Patent: February 8, 2005Assignee: Oki Electric Industry Co, Ltd.Inventors: Shinji Ohuchi, Harufumi Kobayashi, Yasushi Shiraishi
-
Patent number: 6653218Abstract: A polyimide layer is formed over a semiconductor chip, a rewiring to be connected to each of the electrode pads of the semiconductor chip is formed over the polyimide layer, and a post serving as a terminal is connected to each of the electrode pads via the rewiring, thereby redisposing the electrode pads. A resin for encapsulating the rewirings and the posts is formed on the surface of the semiconductor chip to the extent equivalent to the dimension of the semiconductor chip, and in a groove formed in portions of the resin, around the respective posts, the topmost surface and the sidewall face of the respective posts are exposed out of the resin.Type: GrantFiled: November 5, 2002Date of Patent: November 25, 2003Assignee: Oki Electric Industry Co, Ltd.Inventors: Shinji Ohuchi, Harufumi Kobayashi, Yasushi Shiraishi
-
Patent number: 6573598Abstract: A semiconductor device is disclosed which includes a semiconductor chip having a plurality of electrode pads on its upper surface; terminals such as copper posts formed on the upper surface of the semiconductor chip, and electrically connected to each of the electrode pads; a resin deposited on the upper surface of the semiconductor chip, encapsulating the terminals but exposing at least some of them to a predetermined height; and electroconductor members such as solder balls connected to the terminals. There is also disclosed a method of fabricating such a semiconductor device.Type: GrantFiled: April 4, 2000Date of Patent: June 3, 2003Assignee: Oki Electric Industry Co, Ltd.Inventors: Shinji Ohuchi, Harufumi Kobayashi, Yasushi Shiraishi
-
Publication number: 20030092219Abstract: There is disclosed a semiconductor device, comprising: a semiconductor chip having a plurality of electrode pads on the upper surface; a terminal formed on the upper surface of the semiconductor chip, and electrically connected to each of the electrode pads; a resin formed on the upper surface of the semiconductor chip, encapsulating the terminal to be exposed to the extent of a predetermined height; and an electroconductor connected to the terminal. There is also disclosed a method of fabricating such a semiconductor device.Type: ApplicationFiled: November 27, 2002Publication date: May 15, 2003Applicant: Oki Electric Industry Co., Ltd.Inventors: Shinji Ohuchi, Harufumi Kobayashi, Yasushi Shiraishi
-
Publication number: 20030071352Abstract: A polyimide layer is formed over a semiconductor chip, a rewiring to be connected to each of the electrode pads of the semiconductor chip is formed over the polyimide layer, and a post serving as a terminal is connected to each of the electrode pads via the rewiring, thereby redisposing the electrode pads. A resin for encapsulating the rewirings and the posts is formed on the surface of the semiconductor chip to the extent equivalent to the dimension of the semiconductor chip, and in a groove formed in portions of the resin, around the respective posts, the topmost surface and the sidewall face of the respective posts are exposed out of the resin.Type: ApplicationFiled: November 5, 2002Publication date: April 17, 2003Inventors: Shinji Ohuchi, Harufumi Kobayashi, Yasushi Shiraishi
-
Patent number: 6495916Abstract: A polyimide layer is formed over a semiconductor chip, a rewiring to be connected to each of the electrode pads of the semiconductor chip is formed over the polyimide layer, and a post serving as a terminal is connected to each of the electrode pads via the rewiring, thereby redisposing the electrode pads. A resin for encapsulating the rewirings and the posts is formed on the surface of the semiconductor chip to the extent equivalent to the dimension of the semiconductor chip, and in a groove formed in portions of the resin, around the respective posts, the topmost surface and the sidewall face of the respective posts are exposed out of the resin.Type: GrantFiled: November 5, 1999Date of Patent: December 17, 2002Assignee: Oki Electric Industry Co., Ltd.Inventors: Shinji Ohuchi, Harufumi Kobayashi, Yasushi Shiraishi
-
Publication number: 20020167085Abstract: There is disclosed a semiconductor device, comprising: a semiconductor chip having a plurality of electrode pads on the upper surface; a terminal formed on the upper surface of the semiconductor chip, and electrically connected to each of the electrode pads; a resin formed on the upper surface of the semiconductor chip, encapsulating the terminal to be exposed to the extent of a predetermined height; and an electroconductor connected to the terminal. There is also disclosed a method of fabricating such a semiconductor device.Type: ApplicationFiled: April 4, 2000Publication date: November 14, 2002Inventors: Shinji Ohuchi, Harufumi Kobayashi, Yasushi Shiraishi
-
Patent number: 6369440Abstract: A semiconductor apparatus substrate according to the present invention has a substrate, a piece-substrate that has been punched out of the substrate and pushed back to the original position, an opening unit formed in a region of the substrate that substantially surrounds the piece-substrate, and a support unit installed inside the opening unit. As a result of this configuration, in transporting the semiconductor apparatus substrate after the piece-substrate has been pushed back, the piece-substrate is prevented from falling off the semiconductor apparatus substrate.Type: GrantFiled: March 10, 1999Date of Patent: April 9, 2002Assignee: Oki Electric Industry Co, Ltd.Inventor: Harufumi Kobayashi
-
Patent number: 6054757Abstract: A semiconductor apparatus includes a semiconductor chip contained in a package; a first set of connection terminals, of which one ends are connected to the semiconductor chip and the other ends are connected onto a first connection plane outside of the package; and a second set of connection terminals, of which one ends are connected to the semiconductor chip and the other ends are connected onto a second connection plane outside of the package. The first and second connection planes are electrically connected to a circuit board.Type: GrantFiled: February 26, 1998Date of Patent: April 25, 2000Assignee: Oki Electric Industry Co., Ltd.Inventor: Harufumi Kobayashi
-
Patent number: 5952710Abstract: Of ends of a plurality of inner leads disposed around a semiconductor chip shaped substantially in the form of a rectangle, the ends of the inner leads, which correspond to the corners of the rectangle, are provided so as to approach in the direction of the semiconductor chip. Owing to the provision referred to above, bonding wires for connecting electrical connections between the semiconductor chip and the ends of the inner leads can be prevented from drifting upon a mold process.Type: GrantFiled: March 4, 1997Date of Patent: September 14, 1999Assignee: Oki Electric Industry Co., Ltd.Inventor: Harufumi Kobayashi