Abstract: An optical transceiver includes an optical transmitter. The optical transmitter varies the wavelength of its output beam in accordance with the setting of a digital to analog converter. Two split beams emerging respectively from beam splitters are introduced into a photodetector and a wavelength filter, respectively. A quotient is calculated by dividing the digital value output from an analog to digital converter (ADC) by the digital value output from another ADC. A memory address m is then determined based on this quotient without making any calculation for compensating for the imperfect characteristics of the wavelength filter. A wavelength notification value is then selected from a wavelength notification table based on the determined memory address m, and sent to the system host.

Abstract: A control circuit for an optical transmitter/receiver that transmits/receives an optical signal, comprises: a memory having a digital value storage area and an area that stores limit values; a register; an analog/digital conversion circuit that receives analog signals indicating operating parameters of the optical transmitter/receiver, converts the analog signals to respective digital values, and stores the digital values in the memory; a comparison logical circuit that compares the digital values with the limit values, generates flag values, and stores the flag values in the register; and an outside interface that allows an outside host apparatus to access the memory and the register to read the flag values and monitor an operating condition of the optical transmitter/receiver from outside.

Abstract: An optical transceiver performs an optical transmitting and receiving operation, and has a first memory and an external interface. The external interface receives information from a host device and writes the received information in the first memory. The external interface reads the information from the first memory in response to an external command and transfers externally the read information. The information includes at least one of an operation start date, when the optical transceiver starts the optical transmitting and receiving operation, and an operation termination date, when the optical transceiver terminates the optical transmitting and receiving operation.

Abstract: An optical transceiver performs an optical transmitting and receiving operation, and has a first memory and an external interface. The external interface receives information from a host device and writes the received information in the first memory. The external interface reads the information from the first memory in response to an external command and transfers externally the read information. The information includes at least one of an operation start date, when the optical transceiver starts the optical transmitting and receiving operation, and an operation termination dates when the optical transceiver terminates the optical transmitting and receiving operation.

Abstract: An optical transceiver includes an optical transmitter. The optical transmitter varies the wavelength of its output beam in accordance with the setting of a digital to analog converter. Two split beams emerging respectively from beam splitters are introduced into a photodetector and a wavelength filter, respectively. A quotient is calculated by dividing the digital value output from an analog to digital converter (ADC) by the digital value output from another ADC. A memory address m is then determined based on this quotient without making any calculation for compensating for the imperfect characteristics of the wavelength filter. A wavelength notification value is then selected from a wavelength notification table based on the determined memory address m, and sent to the system host.

Abstract: A control circuit for an optical transmitter/receiver that transmits/receives an optical signal, comprises: a memory having a digital value storage area and an area that stores limit values; a register; an analog/digital conversion circuit that receives analog signals indicating operating parameters of the optical transmitter/receiver, converts the analog signals to respective digital values, and stores the digital values in the memory; a comparison logical circuit that compares the digital values with the limit values, generates flag values, and stores the flag values in the register; and an outside interface that allows an outside host apparatus to access the memory and the register to read the flag values and monitor an operating condition of the optical transmitter/receiver from outside.

Abstract: An input buffer circuit without a drop of a capability of a circuit and a limitation of a connection type with a circuit of a former stage is obtained. The output signal (OUTB) is inputted to a first low pass filter circuit, and the first low pass filter circuit integrates the output signal (OUTB). A result of the integration is stored as a voltage value (V2a) in the capacitor (4s). In the same manner, an output signal (OUT) is inputted to a second low pass filter circuit, and the second low pass filter circuit integrates the output signal (OUT). A result of the integration is stored as a voltage value (V2b) in a capacitor (4t). A differential amplifier circuit (5) generates appropriate voltages (V3a and V3b) according to a design specification of the transistors (1x and 1y) by amplifying the voltage values (V2a and V2b) and outputs them. The voltages (V3a and V3b) are impressed on respective back gates of the transistors (1x and 1y), respectively.

Abstract: An input buffer circuit without a drop of a capability of a circuit and a limitation of a connection type with a circuit of a former stage is obtained. The output signal (OUTB) is inputted to a first low pass filter circuit, and the first low pass filter circuit integrates the output signal (OUTB). A result of the integration is stored as a voltage value (V2a) in the capacitor (4s). In the same manner, an output signal (OUT) is inputted to a second low pass filter circuit, and the second low pass filter circuit integrates the output signal (OUT). A result of the integration is stored as a voltage value (V2b) in a capacitor (4t). A differential amplifier circuit (5) generates appropriate voltages (V3a and V3b) according to a design specification of the transistors (1x and 1y) by amplifying the voltage values (V2a and V2b) and outputs them. The voltages (V3a and V3b) are impressed on respective back gates of the transistors (1x and 1y), respectively.

Abstract: A bus circuit comprises a bus interconnection (1) and a plurality of local bus interconnections (10). A plurality of circuit blocks (21a to 21d) are connected to each of the plurality of local bus interconnections (10). A multiplexer (70), a bus driver (60) and a transmitting circuit (80A) are provided corresponding to each of the local bus interconnections (10). Each multiplexer (70) selects one of the outputs from the corresponding plurality of circuit blocks (21a to 21d) and applies the selected one to the bus driver (60). The bus driver (60) drives the bus interconnection (1) according to the output of the multiplexer (70). The local bus interconnections (10) are precharged to a predetermined potential in advance. When any of the plurality of transmitting circuits (80A) is selected, the selected transmitting circuit (80A) either discharges the corresponding local bus interconnection (10) or holds the same at a predetermined potential according to the information on the bus interconnection (1).

Abstract: A digital signal processor includes a digital memory, a controller, an arithmetic operation unit and an interconnecting bus. The memory includes a shift register having an addressable output for storing values which are supplied to a multiplier circuit of the arithmetic operation unit. Use of the shift register provides a data delay minimizing the number of instructions required to implement delay processing. In the arithmetic operation unit, the output from the multiplier is connected to an arithmetic logic unit which, in turn, is connected to an accumulator. The accumulator temporarily stores data from the arithmetic logic unit and output the result onto the data bus. The operations of the signal process are directed by the controller which includes a program memory, an instruction register, and an instruction decoder.

Abstract: An arithmetic operation portion 3 comprises a plurality of multipliers 311 and 312 connected directly with a memory portion 1 so that multiplication processing can be performed in parallel. As a result, the processing capacity for multiplication and addition can be increased and the throughput rate of data can be improved.