Abstract: A clock extraction circuit includes an edge detection unit for detecting a phase at which a trailing edge or a leading edge of input data is coincided with each other, and a phase judgement unit for comparing an edge position of the detected input data and a position of an input clock and for putting a weight, wherein the weight is put so that a shifting amount of the input clock is varied depending on a difference between the edge position of the input data and the position of the input clock.

Abstract: A content addressable memory device capable of correct retrieval operation comprises a flag bit column (12) provided in a memory cell array. The flag bit column (12) stores a flag signal indicating whether a word is in a data written state or an empty state for each word in a data array (2). In the retrieval operation, the data written in the data array (2) and a flag bit column (12) are simultaneously retrieved, providing a correct retrieval result. In addition, since the flag bit column (12) is provided in the memory cell array, it can be controlled in a manner similar to controlling the data array (2).

Abstract: A first comparator compares a voltage of a pair of primary terminals of a pulse transformer with a first reference voltage, to apply an output voltage corresponding to the voltage difference therebetween to a gate of an N channel MOSFET. The N channel MOSFET is responsive to the output voltage for controlling current flowing through a primary side of a pulse transformer. Consequently, even if the impedance of a load connector to a pair of secondary terminals of the pulse transformer is fluctuated, a voltage between the pair of secondary terminals is kept constant. A second comparator compares the output voltage of the first comparator with a second reference voltage, to apply an output voltage corresponding to the voltage difference therebetween to a gate of a P channel MOSFET. When the load impedance becomes low, the P channel MOSFET performs control such that the output voltage of the second comparator does not exceed a predetermined value.

Abstract: A method for producing a three-dimensional type semiconductor device comprises a first semiconductor integrated circuit layer comprising active regions, insulating layers, gate electrodes, and interconnection layers; an insulating layer formed thereon; and a second semiconductor integrated circuit layer comprising active regions, insulating layers, gate electrodes and interconnection layers. Active regions in the second layer are directly coupled to an interconnection layer, and active region and a gate electrode in the first layer, which are located immediately thereunder, by interlayer interconnections through a contact hole formed straight, so that a distance of each interlayer interconnection can be reduced.

Abstract: Programmable Logic Array PLA) cells are arranged at intersections of input lines and output lines of the array. Particular PLA cells to be programmed are arbitrarily selected by word line and bit line decoders. Switches for programming the PLA cells to implement a desired logic function are controlled by data stored in a random access memory whereby programming of the PLA can be changed arbitrarily and during operation of a system including the PLA.

Abstract: An arithmetic unit having true and false deciding circuits (21 to 24) for receiving a first input signal A and a second input signal B to output the second input signal or complement of the same in response to the sign (most significant bit value) of the second input signal. The arithmetic unit further includes an adder (31 to 34) for receiving the first input signal A and output (M) from the true and false deciding circuits to output either A+M or A+M+1 in response to the sign (most significant bit value) of the second input signal B and an AND gate (50) for receiving the most significant bit F.sub.4 of output F from the adder and the most significant bit value B.sub.4 of the second input signal B. The arithmetic unit thus outputs the alternate mark inversion (AMI) code of the input signal B having the output of the AND gate (50) as a high order bit and the most significant bit F.sub.4 of the output F of the adder as a low order bit, with a threshold value of the input signal A.

Abstract: An arithmetic and logic unit control circuit includes arithmetic circuits (10a-10d) for generating the absolute value .vertline.A.vertline. of an input signal A and the complement B of an input signal B from n-bit input signals A and B in response to a control signal from a controller (14). Full adders (6a-6d) add outputs from the arithmetic circuits in response to a control signal from the controller (14). First logic circuits (20a-20c, 21) extract the most significant bit of (.vertline.A.vertline.-B) to form outputs of the full adders (6a-6d) in response to a control signal from controller (14) and second logic circuits (20e, 21) to perform a three-level decision of values A and B from the outputs of the first logic circuits (20a-20c, 21) and the most significant bit of the input signal A. The arithmetic and logic unit can thereby perform Alternate Mark Inversion (AMI) coding in one machine cycle.