Patents by Inventor Haruhiko Harada
Haruhiko Harada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11705344Abstract: A technique capable of shortening process time for plasma cleaning is provided. A method of manufacturing a semiconductor device includes a step of preparing a substrate including a plurality of device regions each including a semiconductor chip electrically connected to a plurality of terminals formed on a main surface by a wire, a step of delivering the substrate while emitting plasma generated in atmospheric pressure to the main surface of the substrate, a step of delivering the substrate while capturing an image of a region of the main surface of the substrate and a step of forming a sealing body by sealing the semiconductor chip and the wire with a resin.Type: GrantFiled: August 18, 2021Date of Patent: July 18, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Masakatsu Suzuki, Haruhiko Harada, Yasuhiko Akaike
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Publication number: 20220068668Abstract: A technique capable of shortening process time for plasma cleaning is provided. A method of manufacturing a semiconductor device includes a step of preparing a substrate including a plurality of device regions each including a semiconductor chip electrically connected to a plurality of terminals formed on a main surface by a wire, a step of delivering the substrate while emitting plasma generated in atmospheric pressure to the main surface of the substrate, a step of delivering the substrate while capturing an image of a region of the main surface of the substrate and a step of forming a sealing body by sealing the semiconductor chip and the wire with a resin.Type: ApplicationFiled: August 18, 2021Publication date: March 3, 2022Inventors: Masakatsu SUZUKI, Haruhiko HARADA, Yasuhiko AKAIKE
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Patent number: 9966329Abstract: Reliability of a semiconductor device is improved. A method for manufacturing the semiconductor device includes the steps of: providing a lead frame having a semiconductor chip mounted thereon; providing a heat radiating frame having a heat radiating plate; and resin sealing the semiconductor chip and the heat radiating plate with the lead frame and the heat radiating frame in a stacked state. The method further includes the steps of: separating a frame body of the heat radiating frame from the lead frame having a sealing body; and applying an inspection to detect resin-unfilled regions to the lead frame having the sealing body. Since the frame body of the heat radiating frame shielding an inspection region is removed before the inspection, it becomes possible to perform the inspection using transmitted light.Type: GrantFiled: July 26, 2017Date of Patent: May 8, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Fukumi Shimizu, Haruhiko Harada
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Publication number: 20180122654Abstract: In a mold die, a tip-end surface of each push-up pin provided on the rear surface side of a lower die cavity block and a part of the rear surface of the lower die cavity block with which the tip-end surface of each push-up pin is contacted are inclined in such a manner that a distance to a top surface of the lower die cavity block becomes longer towards the pot side where mold resin is supplied. When the lower die cavity block is returned to the initial position, the lower die cavity block is lifted while being slightly moved towards the pot block side. No gap is formed between a side surface of the pot block and a side surface of the lower die cavity block.Type: ApplicationFiled: December 28, 2017Publication date: May 3, 2018Inventor: Haruhiko HARADA
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Patent number: 9960055Abstract: In a mold die, a tip-end surface of each push-up pin provided on the rear surface side of a lower die cavity block and a part of the rear surface of the lower die cavity block with which the tip-end surface of each push-up pin is contacted are inclined in such a manner that a distance to a top surface of the lower die cavity block becomes longer towards the pot side where mold resin is supplied. When the lower die cavity block is returned to the initial position, the lower die cavity block is lifted while being slightly moved towards the pot block side. No gap is formed between a side surface of the pot block and a side surface of the lower die cavity block.Type: GrantFiled: December 28, 2017Date of Patent: May 1, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Haruhiko Harada
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Publication number: 20180090423Abstract: Reliability of a semiconductor device is improved. A method for manufacturing the semiconductor device includes the steps of: providing a lead frame having a semiconductor chip mounted thereon; providing a heat radiating frame having a heat radiating plate; and resin sealing the semiconductor chip and the heat radiating plate with the lead frame and the heat radiating frame in a stacked state. The method further includes the steps of: separating a frame body of the heat radiating frame from the lead frame having a sealing body; and applying an inspection to detect resin-unfilled regions to the lead frame having the sealing body. Since the frame body of the heat radiating frame shielding an inspection region is removed before the inspection, it becomes possible to perform the inspection using transmitted light.Type: ApplicationFiled: July 26, 2017Publication date: March 29, 2018Inventors: Fukumi SHIMIZU, Haruhiko HARADA
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Patent number: 9887105Abstract: An object of the present invention is to improve the reliability and productivity of a semiconductor device by suppressing generation of a resin burr in a molding process. In a mold die, a tip-end surface of each push-up pin provided on the rear surface side of a lower die cavity block and a part of the rear surface of the lower die cavity block with which the tip-end surface of each push-up pin is contacted are inclined in such a manner that a distance to a top surface of the lower die cavity block becomes longer towards the pot side where mold resin is supplied. Accordingly, when the lower die cavity block is returned to the initial position, the lower die cavity block is lifted while being slightly moved towards the pot block side. Thus, no gap is formed between a side surface of the pot block and a side surface of the lower die cavity block.Type: GrantFiled: December 29, 2015Date of Patent: February 6, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Haruhiko Harada
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Publication number: 20160211152Abstract: An object of the present invention is to improve the reliability and productivity of a semiconductor device by suppressing generation of a resin burr in a molding process. In a mold die, a tip-end surface of each push-up pin provided on the rear surface side of a lower die cavity block and a part of the rear surface of the lower die cavity block with which the tip-end surface of each push-up pin is contacted are inclined in such a manner that a distance to a top surface of the lower die cavity block becomes longer towards the pot side where mold resin is supplied. Accordingly, when the lower die cavity block is returned to the initial position, the lower die cavity block is lifted while being slightly moved towards the pot block side. Thus, no gap is formed between a side surface of the pot block and a side surface of the lower die cavity block.Type: ApplicationFiled: December 29, 2015Publication date: July 21, 2016Inventor: Haruhiko HARADA
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Patent number: 8435867Abstract: Foreign matter formed over (or adhered to) a surface of a lead is reliably removed. A laser beam is applied to a residual resin (sealing body) which is formed in (or adhered to) a region surrounded by a sealing body (a first sealing body), a lead exposed (projected) from the sealing body, and a dam bar. The foreign matter formed over (or adhered to) the surface of the lead can be reliably removed by washing the surface of the lead after the removal of the residual resin. Thus, in a subsequent plating step, the reliability (wettability, adhesion with the lead) of a plating film to be formed over the surface of the lead can be improved.Type: GrantFiled: September 23, 2010Date of Patent: May 7, 2013Assignee: Renesas Electronics CorporationInventors: Atsushi Fujishima, Haruhiko Harada
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Patent number: 8105878Abstract: A thermosetting tape is adopted as a dicing tape and, after package dicing, the thermosetting tape is heated, then a desired one of divided CSPs is picked up by an inverting collet. Since the thermosetting tape is heated o a predetermined temperature so that its adhesive force becomes zero, the CSP can be picked up by the inverting collet without peeling it off from the thermosetting tape. Thus, peel-off charging does not occur and therefore it is not necessary to perform a destaticizing process. As a result, it is possible to improve the production efficiency in assembling the semiconductor device (CSP).Type: GrantFiled: August 3, 2007Date of Patent: January 31, 2012Assignee: Renesas Electronics CorporationInventors: Haruhiko Harada, Takao Matsuura
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Publication number: 20110097854Abstract: Foreign matter formed over (or adhered to) a surface of a lead is reliably removed. A laser beam is applied to a residual resin (sealing body) which is formed in (or adhered to) a region surrounded by a sealing body (a first sealing body), a lead exposed (projected) from the sealing body, and a dam bar. The foreign matter formed over (or adhered to) the surface of the lead can be reliably removed by washing the surface of the lead after the removal of the residual resin. Thus, in a subsequent plating step, the reliability (wettability, adhesion with the lead) of a plating film to be formed over the surface of the lead can be improved.Type: ApplicationFiled: September 23, 2010Publication date: April 28, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Atsushi FUJISHIMA, Haruhiko HARADA
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Publication number: 20080076210Abstract: A thermosetting tape is adopted as a dicing tape and, after package dicing, the thermosetting tape is heated, then a desired one of divided CSPs is picked up by an inverting collet. Since the thermosetting tape is heated o a predetermined temperature so that its adhesive force becomes zero, the CSP can be picked up by the inverting collet without peeling it off from the thermosetting tape. Thus, peel-off charging does not occur and therefore it is not necessary to perform a destaticizing process. As a result, it is possible to improve the production efficiency in assembling the semiconductor device (CSP).Type: ApplicationFiled: August 3, 2007Publication date: March 27, 2008Inventors: Haruhiko Harada, Takao Matsuura