Abstract: A method and apparatus for synchronous frame communication first communicates a frame signal having communication data and first control information having a bit length and an SDH frame structure in a part of frame time interval and a control information processing method based on an SDH-frame-overhead-process for processing the first control information that includes bytes indicative of each of a relay node's section overhead, an end terminal section overhead, and at least a part of a byte of higher path's overhead. In the frame time interval a signal is communicated by a different second communicating method having the communication data and second control information having a bit length capable of including a significantly higher amount of information than that of the first control information and which corresponds to the first control information byte communicated in the frame time interval.

Abstract: A clock/data recovery circuit used in a receiving apparatus is provided in the circuit including: a voltage control oscillator for generating a clock signal of a frequency of 1/K of a bit rate of an input data signal; a delay circuit; a demultiplexer for demultiplexing the input data signal; a multiplexer for multiplexing the demultiplexed signals; a phase comparator for comparing phases of an output signal of the delay circuit and an output signal of the multiplexer; a lowpass filter; wherein the clock/data recovery circuit outputs the clock signal generated by the voltage control oscillator as a recovery divided clock signal, and outputs the demultiplexed signals output as recovery parallel data signals.

Abstract: In a transmission node, a portion of the control information is separated into M (M is an integer) parts of control information blocks having N (N is an integer) bit length. A control information parity having (8?N) bit length is added to control information block i. The control information block is encoded to M parts of control information having 8 bit length according to a predetermined control information bit array. The control information parity and the control information bit array are set such that Hamming distance of each of the control information code is d, and Hamming distance of the control information 10B code is D (d and D are integers). In a receiving node, the control information code is separated into the control information block and the control information parity. Parity check is performed. When an error is detected, error processing is performed.

Abstract: In a transmission node, a portion of the control information is separated into M (M is an integer) parts of control information blocks having N (N is an integer) bit length. A control information parity having (8-N) bit length is added to control information block i. The control information block is encoded to M parts of control information having 8 bit length according to a predetermined control information bit array. The control information parity and the control information bit array are set such that Hamming distance of each of the control information code is d, and Hamming distance of the control information 10B code is D (d and D are integers). In a receiving node, the control information code is separated into the control information block and the control information parity. Parity check is performed. When an error is detected, error processing is performed.

Abstract: Each of relay nodes 51 to 5M adds a no-disturbance notification information or a code error notification monitoring information to a received signal so as to transmit it. When a code error 7E occurs in a section between a relay nodes 5i−1 and 5i, the relay node 5i−1 transmits a signal 2 containing the monitoring information to which the signal 1 which is transmitted from the transmitting node is added at a predetermined period of time to the relay node 5i. When a code error 7E occurs in the above-mentioned section, the signal 2 includes an errored code which is caused by the code error 7E. The relay node 5i adds the monitoring information to the signal 2 at a predetermined period of time. When the errored code which is caused by the above-mentioned code 7E is detected in a predetermined time, the monitoring information is added thereto after a predetermined time passes. A signal 3 to which the monitoring information is added is received at a receiving node.

Abstract: A clock/data recovery circuit used in a receiving apparatus is provided in the circuit including: a voltage control oscillator for generating a clock signal of a frequency of 1/K of a bit rate of an input data signal; a delay circuit; a demultiplexer for demultiplexing the input data signal; a multiplexer for multiplexing the demultiplexed signals; a phase comparator for comparing phases of an output signal of the delay circuit and an output signal of the multiplexer; a lowpass filter; wherein the clock/data recovery circuit outputs the clock signal generated by the voltage control oscillator as a recovery divided clock signal, and outputs the demultiplexed signals output as recovery parallel data signals.

Abstract: A light emitting unit including a light emitting device of a light emitting module for optical communication is constituted by a laser diode for emitting communication light, a sub-mount having a good thermal conductivity and holding the laser diode on its upper surface, a heat sink for removing the heat generated by the laser diode, a photodiode for monitoring a light output from the laser diode, a laser driver IC which is thermally isolated from the laser diode, has an electric contact placed near the electric contact of the laser diode and connected thereto by wire bonding, and drives the laser diode, and a metal package for holding the heat sink, the photodiode, and the laser driver IC. A light emitting module for optical communication uses the light emitting unit.

Abstract: A photodetector unit for a photodetector module for optical communication includes a photodetector circuit unit constituted by a ceramic board on which a photodiode for converting input light into an electrical signal and a preamplifier IC connected to the photodiode by bump bonding are mounted, and which has a photodetector circuit connected to the preamplifier IC by bump bonding, and a main amplification circuit unit constituted by a ceramic board on which a main amplification IC is mounted, and which has a main amplification circuit connected to the main amplification IC by bump bonding. The ceramic boards of the photodetector circuit unit and the main amplification circuit unit are mechanically and electrically connected to each other such that a mount surface of the preamplifier IC becomes perpendicular to a mount surface of the main amplification IC.

Abstract: An amplifier circuit of this invention includes a first-stage amplifier, an amplifier element connected to the output terminal of the first-stage amplifier as a feedback load, and a further amplifier element connected between the output and input terminals of the amplifier element, and performs negative feedback through a load of the first-stage amplifier. As the amplifier element, a transistor is used, and as the further amplifier element, an emitter-follower transistor is used.