Patents by Inventor Haruhiko Imada

Haruhiko Imada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5761253
    Abstract: A method and an apparatus for enabling a data signal to be transmitted stably at high speed over long distances without using thicker cables and without increasing physical quantities of such resources as transmitting-receiving circuit elements are disclosed. On the transmitting side, the phase of a clock signal relative to the data signal is modified in accordance with the distance between the transmitting and the receiving sides, the clock signal being transmitted along with the data signal. On the receiving side, the incoming data signal is received in synchronism with the received clock signal.
    Type: Grant
    Filed: June 30, 1994
    Date of Patent: June 2, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Yuzuru Fujita, Haruhiko Imada, Seiichi Kawashima
  • Patent number: 5291419
    Abstract: A method for evaluating the life of a connection between members including the steps of extracting parameters defining the shearing strain of a predetermined model representing the connection thereby to calculate the values of plural shearing strains of the connection, calculating the equivalent strain amplitude corresponding to thermal fatigue stress for each of the values of the plural shearing strains defining the relationship between the shearing strain and the equivalent strain amplitude, formulating a life evaluation criterion equation expressed using the equivalent strain amplitude, calculating, for the connection, the equivalent strain amplitude corresponding to each of the shearing strains actually measured using the equation, and substituting the equivalent strain amplitude for the life evaluation criterion equation to acquire the life of the connection.
    Type: Grant
    Filed: January 6, 1992
    Date of Patent: March 1, 1994
    Assignees: Hitachi, Ltd., Hitachi Microcomputer Engineering Ltd.
    Inventors: Ryohei Satoh, Katsuhiro Arakawa, Kiyoshi Kanai, Tsutomu Takahashi, Takaji Takenaka, Haruhiko Imada
  • Patent number: 4706165
    Abstract: In a multilayer circuit board wherein a plurality of electronic parts are provided on a first principal plane, a plurality of brazing pads for pins are respectively arranged on a second principal plane and a plurality of wiring layers having wiring nets for connecting said electrical parts are formed between these principal planes. The EC pads for I/O leads for connecting discrete wires is provided to said first principal plane. EC pads are provided on said second principal plane and are connected to the brazing pads for pins in such a manner as to be electrically separable as required. The EC pads for I/O leads and the brazing pads for pins are connected through the interior of the multilayer circuit board and the EC pads are connected to the wiring net through the interior of the multilayer circuit board.
    Type: Grant
    Filed: October 15, 1986
    Date of Patent: November 10, 1987
    Assignees: Hitachi Microcomputer Engineering Co., Ltd., Hitachi, Ltd.
    Inventors: Takaji Takenaka, Hideki Watanabe, Haruhiko Imada