Abstract: A non-volatile memory device comprises a memory area including a memory cell, and a peripheral area including a circuit that drives the memory cell. The circuit includes a first resistance element. The first resistance element includes a first conductive layer extending in a first direction, a first insulating layer provided on the first conductive layer, and a second conductive layer that includes a portion provided on the first insulating layer and an end portion in contact with the first conductive layer.

Abstract: A non-volatile memory device comprises a memory area including a memory cell, and a peripheral area including a circuit that drives the memory cell. The circuit includes a first resistance element. The first resistance element includes a first conductive layer extending in a first direction, a first insulating layer provided on the first conductive layer, and a second conductive layer that includes a portion provided on the first insulating layer and an end portion in contact with the first conductive layer.

Abstract: A semiconductor device according to one embodiment includes a semiconductor substrate, an insulating member provided in a first region on the semiconductor substrate, an insulating film provided in a second region not provided with the insulating member on the semiconductor substrate, a conductive member provided on the insulating member and on the insulating film, and a first and a second vias connected to the conductive member. An upper surface of the insulating film is lower than an upper surface of the insulating member. An upper part of the conductive member is provided in both the first region and the second region, and a lower part is provided in the second region and not provided in the first region. The conductive member has at least one portion located on the first region between the first via and the second via.

Abstract: A gas circuit breaker includes a sealed tank that includes first and second conductor containers with an insulating tube therebetween and is filled with insulating gas; a fixed arcing contact on the first conductor container side; a movable arcing contact that is provided on the second conductor container side and moves to be able to contact and separate from the fixed arcing contact; a fixed conductive contact on the first conductor container side; a movable conductive contact that moves in accordance with contact and separation of the movable arcing contact and contacts and separates from the fixed conductive contact; and a puffer unit that is provided on the second conductor container side and has a mechanical puffer chamber accommodating the movable conductive contact formed therein, wherein the puffer unit is arranged between the insulating tube and the second conductor container and is exposed to the periphery of the sealed tank.

Abstract: An inrush-current suppressing device includes a residual-magnetic-flux calculation unit that obtains a residual magnetic flux generated within a three-phase transformer, an input magnetic-flux-error calculation unit that obtains a closing-phase input magnetic-flux error, a closing-order determination unit that determines a closing order of phases of a three-phase breaker, a target-closing-phase/time setting unit that sets a time from a reference point to a target closing phase of a first closing phase as a first target closing time, and sets a time obtained by adding up a time from the reference point to a target closing phase of a second closing phase and a delay time set to exclude a period in which a magnetic flux in the first closing phase possibly saturates as a second target closing time, and a closing control unit that generates and outputs a closing control signal to close each phase at the target closing time.

Abstract: A semiconductor memory device includes a source region, a drain region, a channel region, a charge storage layer, and a control gate electrode. The source region and drain region are formed separately from each other in a surface of a semiconductor substrate. The channel region is formed in the semiconductor substrate and located between the source region and the drain region. The charge storage layer is formed on the channel region with a first insulating film interposed therebetween. The control gate electrode is formed on the charge storage layer with a second insulating film interposed therebetween. The control gate has an upper corner portion rounded with a radius of curvature of 5 nm or more.

Abstract: A gas circuit breaker includes a sealed tank that includes first and second conductor containers with an insulating tube therebetween and is filled with insulating gas; a fixed arcing contact on the first conductor container side; a movable arcing contact that is provided on the second conductor container side and moves to be able to contact and separate from the fixed arcing contact; a fixed conductive contact on the first conductor container side; a movable conductive contact that moves in accordance with contact and separation of the movable arcing contact and contacts and separates from the fixed conductive contact; and a puffer unit that is provided on the second conductor container side and has a mechanical puffer chamber accommodating the movable conductive contact formed therein, wherein the puffer unit is arranged between the insulating tube and the second conductor container and is exposed to the periphery of the sealed tank.

Abstract: In one embodiment, a semiconductor device includes a resistor element and a stacked-gate type memory cell transistor. The resistor element includes a first conductive layer which is formed on a second conductive layer via a first insulating layer, and is electrically connected to an interconnect, the second conductive layer being on a substrate and in a floating state. The stacked-gate type memory cell transistor is on the substrate, and includes a floating gate formed of the same material as the second conductive layer.

Abstract: An inrush-current suppressing device includes a residual-magnetic-flux calculation unit that obtains a residual magnetic flux generated within a three-phase transformer, an input magnetic-flux-error calculation unit that obtains a closing-phase input magnetic-flux error, a closing-order determination unit that determines a closing order of phases of a three-phase breaker, a target-closing-phase/time setting unit that sets a time from a reference point to a target closing phase of a first closing phase as a first target closing time, and sets a time obtained by adding up a time from the reference point to a target closing phase of a second closing phase and a delay time set to exclude a period in which a magnetic flux in the first closing phase possibly saturates as a second target closing time, and a closing control unit that generates and outputs a closing control signal to close each phase at the target closing time.

Abstract: A lack of exposure margin is avoided in a region, where an interconnection is required in a direction different from that of an interconnection of a region where an exposure condition is optimized. A semiconductor device According to an aspect of the invention includes a semiconductor substrate 201; an interlayer insulating film 202 that is formed on the semiconductor substrate 201; a plurality of first interconnections 1, 1, . . . that are formed in a first region on the interlayer insulating film 202 while complying with a first design rule, the first interconnections running along a specific direction; a plurality of second interconnections 2, 2, . . . that are formed in a second region on the interlayer insulating film 202 while complying with a second design rule identical to the first design rule, the second interconnections running along the same direction with that of the first interconnections 1, 1, . . .

Abstract: A peripheral circuit area is formed around a memory cell array area. The peripheral circuit area has element regions, an element isolation region isolating the element regions, and field-effect transistor formed in each of the element regions and including a gate electrode extending in a channel width direction, on a semiconductor substrate. An end portion and a corner portion of the gate electrode are on the element isolation region. A radius of curvature of the corner portion of the gate electrode is smaller than a length from the end portion of the element region in the channel width direction to the end portion of the gate electrode in the channel width direction, and is less than 85 nm.

Abstract: A semiconductor memory device includes first and second element regions having a rectangular bent portion and a pair of straight line portions connected to both ends of the bent portions, respectively. The pair of straight line portions extends in an opposite direction each other along a first direction. A first element region is arranged in parallel with the second element region so that the first and second element regions are isolated by an element isolation region, and the first and second bent portions are arranged along a second direction in which the first direction intersects with the second direction at an acute angle. A select gate line connected to select transistors extends in the second direction. A plurality of word lines connected to the memory cells are arranged in parallel with the select gate line in an opposite side of the bent portions with respect to the select gate line.

Abstract: In one embodiment, a semiconductor device includes a resistor element and a stacked-gate type memory cell transistor. The resistor element includes a first conductive layer which is formed on a second conductive layer via a first insulating layer, and is electrically connected to an interconnect, the second conductive layer being on a substrate and in a floating state. The stacked-gate type memory cell transistor is on the substrate, and includes a floating gate formed of the same material as the second conductive layer.

Abstract: A residual-magnetic-flux calculating unit includes a voltage-change-rate detecting unit that detects a transformer-voltage change rate from a phase voltage between a breaker and a transformer, a residual-magnetic-flux detecting unit that detects a residual magnetic flux remaining on the transformer based on the phase voltage, and a breaker-switching-state identifying unit that detects a switching state of the breaker. The residual-magnetic-flux calculating unit recalculates the residual magnetic flux based on the transformer-voltage change rate and a predetermined threshold while the breaker is in an open state.

Abstract: A semiconductor memory device includes a source region, a drain region, a channel region, a charge storage layer, and a control gate electrode. The source region and drain region are formed separately from each other in a surface of a semiconductor substrate. The channel region is formed in the semiconductor substrate and located between the source region and the drain region. The charge storage layer is formed on the channel region with a first insulating film interposed therebetween. The control gate electrode is formed on the charge storage layer with a second insulating film interposed therebetween. The control gate has an upper corner portion rounded with a radius of curvature of 5 nm or more.

Abstract: A semiconductor memory device includes a source region, a drain region, a channel region, a charge storage layer, and a control gate electrode. The source region and drain region are formed separately from each other in a surface of a semiconductor substrate. The channel region is formed in the semiconductor substrate and located between the source region and the drain region. The charge storage layer is formed on the channel region with a first insulating film interposed therebetween. The control gate electrode is formed on the charge storage layer with a second insulating film interposed therebetween. The control gate has an upper corner portion rounded with a radius of curvature of 5 nm or more.

Abstract: In a semiconductor device manufacturing method, a surface of a substrate structure including a semiconductor layer is covered with a first film including first and second openings. The first opening is configured as an alignment mark. The second opening is configured as an opening for introducing an impurity into a first predetermined position of the semiconductor layer. In this method, a third opening is formed in the first film, using a photo mask aligned with the first opening used as an alignment mark. The third opening is configured as an opening for introducing an impurity into a second predetermined position of the semiconductor layer.

Abstract: In a phase control switching device that controls a closing phase of a three-phase switching device connected between a power-supply-side transmission line and a compensation transmission line having a shunt reactor, a closing-phase control unit operates based on a closing command to the three-phase switching device, generates, for each phase, a closing phase in which the three-phase switching device is closed at zero points, both polarities of which are inverted into the same polarity, among zero points where zero points of a voltage changing ratio and zero points of the shunt reactor current coincide with each other, and controls the three-phase switching device.

Abstract: A semiconductor memory device includes a well layer having a first conductivity type and formed in a semiconductor substrate, a block layer formed in a trench and formed of an insulating layer, a gate electrode formed on the semiconductor substrate apart from the block layer, a first diffusion layer having a second conductivity type, formed on a surface of the semiconductor substrate, and having a high impurity concentration region to a first depth from the surface of the semiconductor substrate, a second diffusion layer having the second conductivity type, formed on the surface of the semiconductor substrate on a side of the block layer away from the gate electrode, having a high impurity concentration region to a second depth greater than the first depth from the surface of the semiconductor substrate, and electrically connected to the first diffusion layer, and a contact connected to the second diffusion layer.

Abstract: A semiconductor memory device includes first and second element regions having a rectangular bent portion and a pair of straight line portions connected to both ends of the bent portions, respectively. The pair of straight line portions extends in an opposite direction each other along a first direction. A first element region is arranged in parallel with the second element region so that the first and second element regions are isolated by an element isolation region, and the first and second bent portions are arranged along a second direction in which the first direction intersects with the second direction at an acute angle. A select gate line connected to select transistors extends in the second direction. A plurality of word lines connected to the memory cells are arranged in parallel with the select gate line in an opposite side of the bent portions with respect to the select gate line.