Patents by Inventor Haruhiko Otsuka

Haruhiko Otsuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7271619
    Abstract: Operation noise and charge error of a charge pump circuit are reduced, thereby the jitter characteristics and the spectrum characteristics of a PLL circuit are improved, and further a time period elapsed until the PLL circuit is locked is shortened. The charge pump circuit 36 receives a control signal depending on an output of a phase comparison circuit 34 from a control circuit 35, and comprises a first P-channel MOS transistor P1, a second P-channel MOS transistor P2 and a third P-channel MOS transistor P3, and a first N-channel MOS transistor N1, a second N-channel MOS transistor N2 and a third N-channel MOS transistor N3, and a first current source 61, a second current source 62, a third current source 63 and a fourth current source 64.
    Type: Grant
    Filed: April 18, 2005
    Date of Patent: September 18, 2007
    Assignee: Seiko NPC Corporation
    Inventors: Hiroshi Kawago, Haruhiko Otsuka
  • Publication number: 20050237092
    Abstract: Operation noise and charge error of a charge pump circuit are reduced, thereby the jitter characteristics and the spectrum characteristics of a PLL circuit are improved, and further a time period elapsed until the PLL circuit is locked is shortened. The charge pump circuit 36 receives a control signal depending on an output of a phase comparison circuit 34 from a control circuit 35, and comprises a first P-channel MOS transistor P1, a second P-channel MOS transistor P2 and a third P-channel MOS transistor P3, and a first N-channel MOS transistor N1, a second N-channel MOS transistor N2 and a third N-channel MOS transistor N3, and a first current source 61, a second current source 62, a third current source 63 and a fourth current source 64.
    Type: Application
    Filed: April 18, 2005
    Publication date: October 27, 2005
    Inventors: Hiroshi Kawago, Haruhiko Otsuka
  • Patent number: 6346862
    Abstract: In a quartz oscillation circuit, electric current flowing through a quartz oscillator is reduced. Resistors Rg and Rd are provided respectively in any of paths formed by an output terminal, a capacitance element Cd and a power supply terminal VDD of a CMOS inverter 2 and any of paths formed by an input terminal, a capacitance element Cg and a power supply terminal VDD, thereby reducing a current flowing through a quartz oscillator. In particular, the total value of the resistors Rd and Rg is determined in a range of from 10&OHgr; to 320&OHgr;, thereby reducing a quartz current and obtaining a required negative resistance.
    Type: Grant
    Filed: March 5, 1999
    Date of Patent: February 12, 2002
    Assignee: Nippon Precision Circuits, Inc.
    Inventors: Eiichi Hasegawa, Haruhiko Otsuka
  • Publication number: 20010038319
    Abstract: In a quartz oscillation circuit, electric current flowing through a quartz oscillator is reduced. Resistors Rg and Rd are provided respectively in any of paths formed by an output terminal, a capacitance element Cd and a power supply terminal VDD of a CMOS inverter 2 and any of paths formed by an input terminal, a capacitance element Cg and a power supply terminal VDD, thereby reducing a current flowing through a quartz oscillator. In particular, the total value of the resistors Rd and Rg is determined in a range of from 10 &OHgr; to 320 &OHgr;, thereby reducing a quartz current and obtaining a required negative resistance.
    Type: Application
    Filed: March 5, 1999
    Publication date: November 8, 2001
    Inventors: EIICHI HASEGAWA, HARUHIKO OTSUKA
  • Patent number: 6215370
    Abstract: A crystal oscillator circuit includes a CMOS invertor having an input terminal and an output terminal, a crystal resonator connected between the input terminal and the output terminal respectively at a first connection node and a second connection node, and a feedback resistor connected between the input terminal and the output terminal of the CMOS invertor. A first capacitor is provided between the first connection node and a power source terminal at a predetermined potential and a second capacitor is provided between the second connection node and a power source terminal at the predetermined potential. At least one resistor is disposed in series with at least one of the first capacitor and the second capacitor and has a resistance so as to limit a crystal current in the crystal resonator while maintaining negative resistance for stable oscillation. In an embodiment, a resistor is provided in series with each capacitor.
    Type: Grant
    Filed: January 8, 1998
    Date of Patent: April 10, 2001
    Assignee: Nippon Precision Circuits Inc.
    Inventors: Eiichi Hasegawa, Haruhiko Otsuka
  • Patent number: 5582027
    Abstract: The module integrated type refrigerant condenser includes a roughly cylindrical right side header connected to the outlets of a plurality of condensing tubes and the inlets of a plurality of supercooling tubes, and a modulator directly connected to the right side header in the width direction of the core. By providing a partition part for dividing the second inner space into two gas-liquid separation chambers, the modulator is formed into a shape as if two roughly cylindrical pipe bodies were stacked up in the thickness direction of the core, and the width thereof is made shorter in comparison with a simple, cylindrical modulator.
    Type: Grant
    Filed: March 29, 1995
    Date of Patent: December 10, 1996
    Assignee: Nippondenso Co., Ltd.
    Inventors: Norimasa Baba, Ken Yamamoto, Michiyasu Yamamoto, Yasushi Yamanaka, Hiroki Matsuo, Haruhiko Otsuka, Yoshitaka Kuroda, Kiyoshi Kittaka
  • Patent number: 5549954
    Abstract: A magnetic disc having one or multiple undercoat layers, a continuous thin film magnetic layer or continuous thin film multiple magnetic layers, a protective layer and a lubricant layer sequentially laminated on a non-magnetic disc substrate, which has surface roughness on the surface of the magnetic disc, said surface roughness being such that when the surface roughness is measured by an atomic force microscope or a scanning tunnel microscope, the maximum peak height is from 150 .ANG. to 800 .ANG. based on the height giving the highest frequency in the height distribution of the surface roughness, and the depth (D.sub.0.5) at a bearing ratio of 0.5% from the highest point is from 80 .ANG. to 450 .ANG..
    Type: Grant
    Filed: August 31, 1994
    Date of Patent: August 27, 1996
    Assignee: AG Technology Co., Ltd.
    Inventors: Haruhiko Otsuka, Yuzo Murayama, Akihiko Tashiro, Kyoko Hyomi, Naohiko Ishimaru
  • Patent number: 5534357
    Abstract: A brazing sheet for vacuum brazing is provided wherein the sheet is cladded with an aluminum alloy brazing filler metal having a content of Mg sufficient for vacuum brazing but less than 1.2 wt. % and wherein the Mg.sub.2 Si particle size among Mg contained in the metal is not more than 5 .mu.m as a typical value.
    Type: Grant
    Filed: March 6, 1995
    Date of Patent: July 9, 1996
    Assignee: Nippondenso Co., Ltd.
    Inventors: Tatsuhiko Nonoyama, Shoei Teshima, Haruhiko Otsuka, Yasuyuki Tanaka, Kouji Hiragami
  • Patent number: 4821531
    Abstract: A structural arrangement for an evaporator producing a uniform temperature gradient across its width. The structure is arranged so as to even out the flow of refrigerant within the evaporator. A first tank portion has a inlet and a second tank portion has a outlet. One end of each of plural tubes are connected thereto. A plurality of tubes allow refrigerant to flow from the first tank portion to the second. The tubes are arranged so as to provide equal flow distances for refrigerant across the evaporator, taking into account the directions of flow in the first and second tank portions. In a second embodiment, the inlet port and the outlet port are disposed at the first tank portion and the second tank portion respectively in such a manner that directions of the refrigerant flow within the first tank portion and the second tank portion are opposite to each other.
    Type: Grant
    Filed: December 9, 1987
    Date of Patent: April 18, 1989
    Assignee: Nippondenso Co., Ltd.
    Inventors: Yoshiyuki Yamauchi, Toshio Ohhara, Shinji Ogawa, Isao Kuroyanagi, Haruhiko Otsuka, Toshio Takahashi, Osamu Kasebe