Patents by Inventor Haruhiko Sakai
Haruhiko Sakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10941787Abstract: A power source integrated vacuum pump configured such that a pump main body and a pump power source device are integrated together, comprises: a substrate which is provided at the pump power source device and on which an electronic component is mounted; a cooling device having a cooling surface fixed in contact with the substrate; and a heat insulating member having a smaller coefficient of thermal conductivity than that of a material forming the cooling surface and covering a cooling surface region to which the substrate is not fixed.Type: GrantFiled: April 9, 2018Date of Patent: March 9, 2021Assignee: SHIMADZU CORPORATIONInventors: Haruhiko Sakai, Nobuhiko Moriyama
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Publication number: 20180306204Abstract: A power source integrated vacuum pump configured such that a pump main body and a pump power source device are integrated together, comprises: a substrate which is provided at the pump power source device and on which an electronic component is mounted; a cooling device having a cooling surface fixed in contact with the substrate; and a heat insulating member having a smaller coefficient of thermal conductivity than that of a material forming the cooling surface and covering a cooling surface region to which the substrate is not fixed.Type: ApplicationFiled: April 9, 2018Publication date: October 25, 2018Inventors: Haruhiko SAKAI, Nobuhiko MORIYAMA
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Publication number: 20160369844Abstract: A slide rail includes: an outer rail; an inner rail, including a space into which a guide pin, which is attached to a to-be-mounted object, is capable of being inserted from one end side of the inner rail, configured to slide in a longitudinal direction of the outer rail; and a locking mechanism configured to fix the inner rail onto the outer rail.Type: ApplicationFiled: June 1, 2016Publication date: December 22, 2016Applicant: FUJITSU LIMITEDInventors: Hisashi ITO, Nobuhiro OGAWA, Tatsuya Sudo, HIROSHI TAKAHASHI, Michi AMANAI, Kosuke Nakamura, Haruhiko Sakai
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Publication number: 20150356042Abstract: A computer system including a peripheral device including at least one of an input device and an output device; a plurality of computers; and a switching device that includes a plurality of connectors and a memory, the plurality of connectors including a connector group to which the plurality of computers are coupled and an input-output connector to which the peripheral device is coupled, the switching device coupling one connector of the connector group and the input-output connector, wherein the switching device is configured to: receive identification data for identifying a computer; and connect the input-output connector and a first connector of the connector group, the first connector being represented by a first connector identifier having been associated with the received identification data and stored in the memory, when the received identification data has been stored in the memory.Type: ApplicationFiled: April 14, 2015Publication date: December 10, 2015Applicant: FUJITSU LIMITEDInventors: Shingo Ochiai, Haruhiko Sakai
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Patent number: 8241958Abstract: To provide a semiconductor device and a semiconductor module in which breakage of a semiconductor element due to a pressing force given from the outside is prevented. A semiconductor device according to the present invention has a configuration mainly including an island, a semiconductor element mounted on a front surface of the island, a lead that functions as an external connection terminal, and a sealing resin that covers these components in an integrated manner and mechanically supports them. Further, a through-hole is provided so as to penetrate the sealing resin. A front surface of the sealing resin around the through-hole forms a flat part. The front surface of the sealing resin that overlaps the semiconductor element is depressed inward with respect to the flat part to form a depressed part.Type: GrantFiled: October 14, 2010Date of Patent: August 14, 2012Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLCInventor: Haruhiko Sakai
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Publication number: 20110024883Abstract: To provide a semiconductor device and a semiconductor module in which breakage of a semiconductor element due to a pressing force given from the outside is prevented. A semiconductor device according to the present invention has a configuration mainly including an island, a semiconductor element mounted on a front surface of the island, a lead that functions as an external connection terminal, and a sealing resin that covers these components in an integrated manner and mechanically supports them. Further, a through-hole is provided so as to penetrate the sealing resin. A front surface of the sealing resin around the through-hole forms a flat part. The front surface of the sealing resin that overlaps the semiconductor element is depressed inward with respect to the flat part to form a depressed part.Type: ApplicationFiled: October 14, 2010Publication date: February 3, 2011Applicants: SANYO Electric Co., Ltd.Inventor: Haruhiko SAKAI
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Patent number: 7839004Abstract: To provide a semiconductor device and a semiconductor module in which breakage of a semiconductor element due to a pressing force given from the outside is prevented. A semiconductor device according to the present invention has a configuration mainly including an island, a semiconductor element mounted on a front surface of the island, a lead that functions as an external connection terminal, and a sealing resin that covers these components in an integrated manner and mechanically supports them. Further, a through-hole is provided so as to penetrate the sealing resin. A front surface of the sealing resin around the through-hole forms a flat part. The front surface of the sealing resin that overlaps the semiconductor element is depressed inward with respect to the flat part to form a depressed part.Type: GrantFiled: July 30, 2009Date of Patent: November 23, 2010Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.Inventor: Haruhiko Sakai
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Publication number: 20100025828Abstract: To provide a semiconductor device and a semiconductor module in which breakage of a semiconductor element due to a pressing force given from the outside is prevented. A semiconductor device according to the present invention has a configuration mainly including an island, a semiconductor element mounted on a front surface of the island, a lead that functions as an external connection terminal, and a sealing resin that covers these components in an integrated manner and mechanically supports them. Further, a through-hole is provided so as to penetrate the sealing resin. A front surface of the sealing resin around the through-hole forms a flat part. The front surface of the sealing resin that overlaps the semiconductor element is depressed inward with respect to the flat part to form a depressed part.Type: ApplicationFiled: July 30, 2009Publication date: February 4, 2010Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.Inventor: Haruhiko SAKAI
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Patent number: 7030501Abstract: A conventional one-chip dual MOSFET has a structure in which two chips are arranged side by side and drain electrodes are short-circuited. Therefore, the mounting area thereof is large, and the resistance between the drain electrodes cannot be reduced. Accordingly, there is a limit of reduction in size and thickness of a semiconductor device, which is demanded by the market. A dual MOSFET of the embodiment includes two semiconductor chips (MOSFET) superimposed on each other with drain electrodes thereof directly connected to each other. In the dual MOSFET, the drain electrodes do not need to be led to the outside, and only two gate terminals and two source terminals are used. Accordingly, these four terminals are led out by means of a lead frame or conductive patterns. This allows the device to be reduced in size and to have lower on-resistance.Type: GrantFiled: June 15, 2004Date of Patent: April 18, 2006Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Shigeharu Yoshiba, Hirokazu Fukuda, Haruhiko Sakai
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Publication number: 20050017339Abstract: A conventional one-chip dual MOSFET has a structure in which two chips are arranged side by side and drain electrodes are short-circuited. Therefore, the mounting area thereof is large, and the resistance between the drain electrodes cannot be reduced. Accordingly, there is a limit of reduction in size and thickness of a semiconductor device, which is demanded by the market. A dual MOSFET of the embodiment includes two semiconductor chips (MOSFET) superimposed on each other with drain electrodes thereof directly connected to each other. In the dual MOSFET, the drain electrodes do not need to be led to the outside, and only two gate terminals and two source terminals are used. Accordingly, these four terminals are led out by means of a lead frame or conductive patterns. This allows the device to be reduced in size and to have lower on-resistance.Type: ApplicationFiled: June 15, 2004Publication date: January 27, 2005Inventors: Shigeharu Yoshiba, Hirokazu Fukuda, Haruhiko Sakai
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Patent number: 6833608Abstract: Two different switches with two different signal input schemes are fabricated by mounting the same semiconductor chip on the same lead pattern. Two of the leads of the lead pattern provides space enough for wire-bonding connection to corresponding electrode pads on the semiconductor chip at both ends of the semiconductor chip. Because each of electrode pads can be connected to the corresponding lead at either end of the semiconductor chip, two sets of bonding wire connection between the leads and the electrode pads provides two different switches with two different signal inputs scheme.Type: GrantFiled: November 15, 2002Date of Patent: December 21, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Mikito Sakakibara, Hideyuki Inotsume, Haruhiko Sakai, Shigeo Kimura
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Patent number: 6833616Abstract: A semiconductor chip is mounted on a wiring board that has a two-layer lead structure. One of the leads used for receiving input signals is disposed on the lower layer and runs underneath the semiconductor chip forming an U-shaped wiring line while other leads are disposed on the upper layer. Because one of the upper layer leads for receiving input signals is disposed in the U-shaped pocket of the U-shaped wiring line of the lower layer, the relative positioning of corresponding terminals can be changed into a reversal of the positioning of the electrode pads of the chip connected to the terminals. Furthermore, one of the upper layer lead for receiving control signals is placed between the chip and the lower layer lead underneath the chip to prevent high frequency signal interference.Type: GrantFiled: December 5, 2002Date of Patent: December 21, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Mikito Sakakibara, Hideyuki Inotsume, Haruhiko Sakai, Shigeo Kimura
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Patent number: 6818969Abstract: A semiconductor device includes four input terminals, four leads extending from the corresponding input terminals and a semiconductor chip that has a first circuit and a second circuit and is mounted on one of the leads. The lead having the semiconductor chip thereon bends in a plane of the substrate so that an end portion and a mid portion of the lead are exposed on one side of the semiconductor chip. One of the input electrode pads of the first circuit is connected to the end portion of the lead by a bonding wire. The end portion of the lead is on the opposite side of the mid portion of the lead with respect to one of the leads that is connected to one of the input electrode pads of the second circuit by a bonding wire. This configuration achieves a crossing wiring structure within the packaging. By changing the connection of bonding wires, the crossing wiring structure is easily undone.Type: GrantFiled: October 30, 2002Date of Patent: November 16, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Mikito Sakakibara, Hideyuki Inotsume, Haruhiko Sakai, Shigeo Kimura
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Publication number: 20030151137Abstract: A semiconductor chip is mounted on a wiring board that has a two-layer lead structure. One of the leads used for receiving input signals is disposed on the lower layer and runs underneath the semiconductor chip forming an U-shaped wiring line while other leads are disposed on the upper layer. Because one of the upper layer leads for receiving input signals is disposed in the U-shaped pocket of the U-shaped wiring line of the lower layer, the relative positioning of corresponding terminals can be changed into a reversal of the positioning of the electrode pads of the chip connected to the terminals. Furthermore, one of the upper layer lead for receiving control signals is placed between the chip and the lower layer lead underneath the chip to prevent high frequency signal interference.Type: ApplicationFiled: December 5, 2002Publication date: August 14, 2003Applicant: Sanyo Electric Co., Ltd.Inventors: Tetsuro Asano, Mikito Sakakibara, Hideyuki Inotsume, Haruhiko Sakai, Shigeo Kimura
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Publication number: 20030137044Abstract: Two different switches with two different signal input schemes are fabricated by mounting the same semiconductor chip on the same lead pattern. Two of the leads of the lead pattern provides space enough for wire-bonding connection to corresponding electrode pads on the semiconductor chip at both ends of the semiconductor chip. Because each of electrode pads can be connected to the corresponding lead at either end of the semiconductor chip, two sets of bonding wire connection between the leads and the electrode pads provides two different switches with two different signal inputs scheme.Type: ApplicationFiled: November 15, 2002Publication date: July 24, 2003Inventors: Tetsuro Asano, Mikito Sakakibara, Hideyuki Inotsume, Haruhiko Sakai, Shigeo Kimura
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Publication number: 20030094679Abstract: A semiconductor device includes four input terminals, four leads extending from the corresponding input terminals and a semiconductor chip that has a first circuit and a second circuit and is mounted on one of the leads. The lead having the semiconductor chip thereon bends in a plane of the substrate so that an end portion and a mid portion of the lead are exposed on one side of the semiconductor chip. One of the input electrode pads of the first circuit is connected to the end portion of the lead by a bonding wire. The end portion of the lead is on the opposite side of the rmid portion of the lead with respect to one of the leads that is connected to one of the input electrode pads of the second circuit by a bonding wire. This configuration achieves a crossing wiring structure within the packaging. By changing the connection of bonding wires, the crossing wiring structure is easily undone.Type: ApplicationFiled: October 30, 2002Publication date: May 22, 2003Inventors: Tetsuro Asano, Mikito Sakakibara, Hideyuki Inotsume, Haruhiko Sakai, Shigeo Kimura