Abstract: A photodetecting device 1 includes a photodiode PD and an integrating circuit 10. The integrating circuit 10 includes an amplifier circuit 20, a capacitive element C, a first switch SW1, and a second switch SW2. The second switch SW2 is provided between a reference potential input terminal to which a reference potential Vref is input and a terminal of the capacitive element C on the inverting input terminal side of the amplifier circuit 20, and the second switch is opened or closed according to the level of a second reset signal Reset2, and is capable of applying the reference potential Vref to the terminal of the capacitive element. Thus, an integrating circuit and a photodetecting device capable of achieving both low power consumption and high speed can be realized.

Abstract: A photodetecting device 1 includes a photodiode PD and an integrating circuit 11. The integrating circuit 11 includes an amplifier circuit 20, a capacitive element C2, and a second switch SW2. The amplifier circuit 20 has a driving section including a PMOS transistor T1 and an NMOS transistor T2, the respective drain terminals thereof being connected to each other. A first switch SW1 comprising a PMOS transistor T10 is opened or closed according to the level of a first reset signal Reset1 input to the gate terminal. When the first reset signal Reset1 is at a low level, the first switch SW1 is closed to apply a power supply potential VDD to the gate terminal of the PMOS transistor T1, thereby turning off the PMOS transistor T1. Thus, an amplifier circuit, an integrating circuit and a photodetecting device capable of achieving both low power consumption and high speed can be realized.

Abstract: A solid-state imaging device 1 includes photodiodes PD1 to PDN, charge-voltage converting circuits 101 to 10N, pre-holding circuits 201 to 20N, a transimpedance amplifier 30, a peak holding circuit 50, and a post-holding circuit 60. The charge-voltage converting circuit 10n inputs charges generated at the photodiode PDn and outputs a voltage value corresponding to the input charge quantity. The pre-holding circuit 20n holds the output voltage value from the charge-voltage converting circuit 10n and outputs the output voltage value as a current. The transimpedance amplifier 30 inputs voltage values successively output form the pre-holding circuits 201 to 20N as currents and outputs voltage values converted based on a transimpedance from the currents flowing in accordance with change quantities to the input voltage values from a reference voltage value. The peak holding circuit 50 holds and outputs a peak hold voltage of the output voltage values from the transimpedance amplifier 30.

Abstract: A solid-state imaging device 1 includes N pixel sections 101 to 10N, transimpedance circuits 20a and 20b, integrating circuits 30a and 30b, and a difference arithmetic circuit 40. Each pixel section 10n includes a photoelectric converting circuit including a photodiode, and a first holding circuit and a second holding circuit which hold an output voltage of the photoelectric converting circuit. A voltage held by the first holding circuit of each pixel section 10n is input into the difference arithmetic circuit 40 through a common wire 50a, the transimpedance circuit 20a, and the integrating circuit 30a. A voltage held by the second holding circuit of each pixel section 10n is input into the difference arithmetic circuit 40 through a common wire 50b, the transimpedance circuit 20b, and the integrating circuit 30b. A voltage corresponding to a difference between the voltages output from the integrating circuits 30a and 30b, respectively, is output from the difference arithmetic circuit 40.

Abstract: The present invention relates to a sensor apparatus having a structure capable of obtaining digital values of signal components with a high accuracy using an A/D conversing circuit with the outputted digital value thereof having a small number of expressive bits. In the sensor apparatus, a voltage value corresponding to the amount of incident light to a photodiode is held by a holding circuit through an integrating circuit and a CDS circuit. Meanwhile, a voltage value corresponding to the amount of incident light to an adjacent photodiode is held by another holding circuit through an integrating circuit and a CDS circuit. The voltage values held by the respective different holding circuits are inputted to a subtracting circuit through different paths. The subtracting circuit outputs a voltage value corresponding to the difference between the two inputted voltage values. In an A/D converting section, the difference voltage outputted from the subtracting circuit is converted into a digital value.

Abstract: A photodetecting device 1 includes a photodiode PD and an integrating circuit 11. The integrating circuit 11 includes an amplifier circuit 20, a capacitive element C2, and a second switch SW2. The amplifier circuit 20 has a driving section including a PMOS transistor T1 and an NMOS transistor T2, the respective drain terminals thereof being connected to each other. A first switch SW1 comprising a PMOS transistor T10 is opened or closed according to the level of a first reset signal Reset1 input to the gate terminal. When the first reset signal Reset1 is at a low level, the first switch SW1 is closed to apply a power supply potential VDD to the gate terminal of the PMOS transistor T1, thereby turning off the PMOS transistor T1. Thus, an amplifier circuit, an integrating circuit and a photodetecting device capable of achieving both low power consumption and high speed can be realized.

Abstract: A photodetecting device 1 includes a photodiode PD and an integrating circuit 10. The integrating circuit 10 includes an amplifier circuit 20, a capacitive element C, a first switch SW1, and a second switch SW2. The second switch SW2 is provided between a reference potential input terminal to which a reference potential Vref is input and a terminal of the capacitive element C on the inverting input terminal side of the amplifier circuit 20, and the second switch is opened or closed according to the level of a second reset signal Reset2, and is capable of applying the reference potential Vref to the terminal of the capacitive element. Thus, an integrating circuit and a photodetecting device capable of achieving both low power consumption and high speed can be realized.

Abstract: A photodetector of a wide dynamic range of incident light amount detection and low temperature dependence is provided. A first signal processing unit 10m,n includes an integrating circuit 11, a first holding circuit 12, a comparing circuit 13, a second holding circuit 14, and a latching circuit 15. The integrating circuit 11 has a variable capacitor unit that is selectively set to a capacitance value among a plurality of capacitance values, accumulates charges, output from the photodiode, into the variable capacitor unit over an accumulating period that is in accordance with the capacitance value set at the variable capacitor unit, and outputs a voltage V1 that is in accordance with the amount of the accumulated charges.

Abstract: The present invention relates to a sensor apparatus having a structure capable of obtaining digital values of signal components with a high accuracy using an A/D conversing circuit with the outputted digital value thereof having a small number of expressive bits. In the sensor apparatus, a voltage value corresponding to the amount of incident light to a photodiode is held by a holding circuit through an integrating circuit and a CDS circuit. Meanwhile, a voltage value corresponding to the amount of incident light to an adjacent photodiode is held by another holding circuit through an integrating circuit and a CDS circuit. The voltage values held by the respective different holding circuits are inputted to a subtracting circuit through different paths. The subtracting circuit outputs a voltage value corresponding to the difference between the two inputted voltage values. In an A/D converting section, the difference voltage outputted from the subtracting circuit is converted into a digital value.

Abstract: The present invention relates to a sensor apparatus having a structure capable of obtaining digital values of signal components with a high accuracy using an A/D conversing circuit with the outputted digital value thereof having a small number of expressive bits. In the sensor apparatus, a voltage value corresponding to the amount of incident light to a photodiode is held by a holding circuit through an integrating circuit and a CDS circuit. Meanwhile, a voltage value corresponding to the amount of incident light to an adjacent photodiode is held by another holding circuit through an integrating circuit and a CDS circuit. The voltage values held by the respective different holding circuits are inputted to a subtracting circuit through different paths. The subtracting circuit outputs a voltage value corresponding to the difference between the two inputted voltage values. In an A/D converting section, the difference voltage outputted from the subtracting circuit is converted into a digital value.

Abstract: The present invention relates to a sensor apparatus having a structure capable of obtaining digital values of signal components with a high accuracy using an A/D conversing circuit with the outputted digital value thereof having a small number of expressive bits. In the sensor apparatus, a voltage value corresponding to the amount of incident light to a photodiode is held by a holding circuit through an integrating circuit and a CDS circuit. Meanwhile, a voltage value corresponding to the amount of incident light to an adjacent photodiode is held by another holding circuit through an integrating circuit and a CDS circuit. The voltage values held by the respective different holding circuits are inputted to a subtracting circuit through different paths. The subtracting circuit outputs a voltage value corresponding to the difference between the two inputted voltage values. In an A/D converting section, the difference voltage outputted from the subtracting circuit is converted into a digital value.

Abstract: A solid-state imaging device 1 includes photodiodes PD1 to PDN, charge-voltage converting circuits 101 to 10N, pre-holding circuits 201 to 20N, a transimpedance amplifier 30, a peak holding circuit 50, and a post-holding circuit 60. The charge-voltage converting circuit 10n inputs charges generated at the photodiode PDn and outputs a voltage value corresponding to the input charge quantity. The pre-holding circuit 20n holds the output voltage value from the charge-voltage converting circuit 10n and outputs the output voltage value as a current. The transimpedance amplifier 30 inputs voltage values successively output form the pre-holding circuits 201 to 20N as currents and outputs voltage values converted based on a transimpedance from the currents flowing in accordance with change quantities to the input voltage values from a reference voltage value. The peak holding circuit 50 holds and outputs a peak hold voltage of the output voltage values from the transimpedance amplifier 30.

Abstract: A solid-state imaging device 1 includes N pixel sections 101 to 10N, transimpedance circuits 20a and 20b, integrating circuits 30a and 30b, and a difference arithmetic circuit 40. Each pixel section 10n includes a photoelectric converting circuit including a photodiode, and a first holding circuit and a second holding circuit which hold an output voltage of the photoelectric converting circuit. A voltage held by the first holding circuit of each pixel section 10n is input into the difference arithmetic circuit 40 through a common wire 50a, the transimpedance circuit 20a, and the integrating circuit 30a. A voltage held by the second holding circuit of each pixel section 10n is input into the difference arithmetic circuit 40 through a common wire 50b, the transimpedance circuit 20b, and the integrating circuit 30b. A voltage corresponding to a difference between the voltages output from the integrating circuits 30a and 30b, respectively, is output from the difference arithmetic circuit 40.

Abstract: A photodetector of a wide dynamic range of incident light amount detection and low temperature dependence is provided. A first signal processing unit 10m,n includes an integrating circuit 11, a first holding circuit 12, a comparing circuit 13, a second holding circuit 14, and a latching circuit 15. The integrating circuit 11 has a variable capacitor unit that is selectively set to a capacitance value among a plurality of capacitance values, accumulates charges, output from the photodiode, into the variable capacitor unit over an accumulating period that is in accordance with the capacitance value set at the variable capacitor unit, and outputs a voltage V1 that is in accordance with the amount of the accumulated charges. The comparing circuit 13 inputs the voltage V1 output from the integrating circuit 11, performs a quantitative comparison of the voltage V1 with a reference voltage Vref, outputs a compared signal S3 expressing the result of comparison, and, when the voltage V1 output from the integrating.

Abstract: The present invention relates to a sensor apparatus having a structure capable of obtaining digital values of signal components with a high accuracy using an A/D conversing circuit with the outputted digital value thereof having a small number of expressive bits. In the sensor apparatus, a voltage value corresponding to the amount of incident light to a photodiode is held by a holding circuit through an integrating circuit and a CDS circuit. Meanwhile, a voltage value corresponding to the amount of incident light to an adjacent photodiode is held by another holding circuit through an integrating circuit and a CDS circuit. The voltage values held by the respective different holding circuits are inputted to a subtracting circuit through different paths. The subtracting circuit outputs a voltage value corresponding to the difference between the two inputted voltage values. In an A/D converting section, the difference voltage outputted from the subtracting circuit is converted into a digital value.

Abstract: A transmission transistor T2 transfers charges generated in a photodiode PD to a first capacitor part C11 via a first switch SW11, and transfers the charges to a second capacitor part C12 via a second switch SW12. An amplification transistor T1 outputs a voltage corresponding to the amount of accumulated charges in at least one of a first capacitor part C11 and a second capacitor part C12, connected to a gate terminal, and a gate terminal of the amplification transistor T1 is connected to at least one of the first capacitor part C11 and the second capacitor part C12.

Abstract: A signal current corresponding to an incident light intensity is output from a photodiode PD, the signal current is converted into a signal voltage by an integration circuit 10, and the amount of a change in signal voltage in a predetermined time is output from a CDS circuit 20. The difference between two voltage values output from the CDS circuit 20 is obtained by a difference arithmetic circuit 30 and held by a S-H circuit 40. In addition, the maximum value of voltage values obtained by the difference arithmetic circuits 30 of respective units 100n is obtained by comparison circuits 50 of the respective units 100n, a reference signal voltage generation circuit 500, a final coincidence determination circuit 200, and a reference voltage hold circuit 300, and on the basis of the maximum value, the A/D conversion range of an A/D conversion circuit 400 is set.

Abstract: The signal current corresponding to an incident light intensity is output from a photodiode, and the integrating circuit stores an electric charge according to the signal current and outputs a signal voltage corresponding to the amount of the stored electric charge. The first CDS circuit stores in the integrating capacitor an electric charge corresponding to a change in the signal voltage output from the integrating circuit. Similarly, the second circuit stores in the integrating capacitor an electric charge corresponding to a change in the signal voltage output from the integrating circuit. The difference calculation circuit determines a difference between the amount of charge stored in the integrating capacitor of the first CDS circuit and the amount of charge stored in the integrating capacitor of the second CDS circuit, and outputs a signal voltage corresponding to the difference.

Abstract: A drive circuit 270 having a differential amplifier 271, a current controller 272 formed from an n-channel MOSFET, and a drive ability control circuit sets its output drive ability in a high state only in a signal read, and otherwise sets the output drive ability in a low state to reduce power consumption. Thus, a solid-state image sensing device which can perform a high-speed read while ensuring low power consumption and wide dynamic range can be implemented. As the drive ability control circuit, for example, a current source 273 formed from an n-channel MOSFET and voltage switching by a drive change-over switch 274 can be used.

Abstract: A signal current corresponding to an incident light intensity is output from a photodiode PD, the signal current is converted into a signal voltage by an integration circuit 10, and the amount of a change in signal voltage in a predetermined time is output from a CDS circuit 20. The difference between two voltage values output from the CDS circuit 20 is obtained by a difference arithmetic circuit 30 and held by a S-H circuit 40. In addition, the maximum value of voltage values obtained by the difference arithmetic circuits 30 of respective units 100n is obtained by comparison circuits 50 of the respective units loon, a reference signal voltage generation circuit 500, a final coincidence determination circuit 200, and a reference voltage hold circuit 300, and on the basis of the maximum value, the A/D conversion range of an A/D conversion circuit 400 is set.