Abstract: A non-transitory computer-readable recording medium storing a program that causes a computer to execute a time synchronization process between a master device and a slave device, the process includes calculating a clock deviation between the master device and the slave device based on a plurality of pieces of time information in each of the master device and the slave device, dividing a difference in the clock deviation, and incorporating each of the divided differences into the time information of the slave device to correct the clock deviation.

Abstract: A transmitter includes a memory, and a processor configured to generate a first clock parallel signal by performing serial-parallel conversion of a first clock signal acquired by using a reference clock and generate a second clock parallel signal by performing serial-parallel conversion of a second clock signal acquired by using the reference clock, generate first compressed information by compressing the first clock parallel signal on the basis of clock periodicity and generate second compressed information by compressing the second clock parallel signal based on the clock periodicity, generate a serial signal by adding a synchronization signal indicating a top of a multiplexed signal to the multiplexed signal generated by time-division multiplexing of the first compressed information and the second compressed information, and transmit the serial signal to a receiver.

Abstract: A non-transitory computer-readable recording medium storing a program that causes a computer to execute a time synchronization process between a master device and a slave device, the process includes calculating a clock deviation between the master device and the slave device based on a plurality of pieces of time information in each of the master device and the slave device, dividing a difference in the clock deviation, and incorporating each of the divided differences into the time information of the slave device to correct the clock deviation.

Abstract: A transmitter includes a memory, and a processor configured to generate a first clock parallel signal by performing serial-parallel conversion of a first clock signal acquired by using a reference clock and generate a second clock parallel signal by performing serial-parallel conversion of a second clock signal acquired by using the reference clock, generate first compressed information by compressing the first clock parallel signal on the basis of clock periodicity and generate second compressed information by compressing the second clock parallel signal based on the clock periodicity, generate a serial signal by adding a synchronization signal indicating a top of a multiplexed signal to the multiplexed signal generated by time-division multiplexing of the first compressed information and the second compressed information, and transmit the serial signal to a receiver.

Abstract: A transmission apparatus configured to extract reception data and a first clock from a received signal and transmit the reception data based on a second clock synchronized with the first clock, the transmission apparatus includes: a detector configured to detect a frequency difference between the first clock and the second clock; a selector configured to select parallel data according to the frequency difference from a plurality of parallel data obtained by shifting bit patterns formed by bits of continuing “0” and continuing “1” by different number of the bits with each other, and a converter configured to convert the parallel data selected by the selector into serial data so as to be the second clock.

Abstract: An optical transmission device includes: a serializer and deserializer configured to convert an input client signal into parallel data at a sampling rate of k times (k is a power of 2) a rate of the input client signal and output the parallel data; a frame generation section configured to generate an optical channel payload unit (OPU) frame from the client signal; and a stuff control section connected to an output of the parallel data and configured to perform, in units of 1/k bits, a stuff operation to map the client signal into the OPU frame and thereby calculate a Cn(n=1/k) value which is a theoretical value of the stuff operation.

Abstract: A transmission apparatus configured to extract reception data and a first clock from a received signal and transmit the reception data based on a second clock synchronized with the first clock, the transmission apparatus includes: a detector configured to detect a frequency difference between the first clock and the second clock; a selector configured to select parallel data according to the frequency difference from a plurality of parallel data obtained by shifting bit patterns formed by bits of continuing “0” and continuing “1” by different number of the bits with each other, and a converter configured to convert the parallel data selected by the selector into serial data so as to be the second clock.

Abstract: An optical transmission device includes: a serializer and deserializer configured to convert an input client signal into parallel data at a sampling rate of k times (k is a power of 2) a rate of the input client signal and output the parallel data; a frame generation section configured to generate an optical channel payload unit (OPU) frame from the client signal; and a stuff control section connected to an output of the parallel data and configured to perform, in units of 1/k bits, a stuff operation to map the client signal into the OPU frame and thereby calculate a Cn(n=1/k) value which is a theoretical value of the stuff operation.

Abstract: A transmission device includes: a detector to detect a head pattern indicating a head of data for each of ports that receives the data; a write controller to write the data to a memory provided for each of the ports, based on a detection timing of the head pattern detected by the detector; a determination unit to determine, among ports for each of which the head pattern has been detected by the detector, a specific port for which a total delay amount is minimum, the total delay amount being a total sum of delay amounts from the head pattern related to the specific port to each of the head patterns related to ports other than the specific port; and a read controller to read the data from the memory, based on the detection timing of the head pattern related to the specific port determined by the determination unit.

Abstract: A configuration controller configured to control configuration of a partially configurable programmable device, includes a determination unit configured to determine whether or not circuit data to be arranged in any one of a plurality of areas in the programmable device matches desired circuit data for which a desired arrangement target area is specified, before the circuit data to be arranged is written into the programmable device, and a data controller configured to control whether or not the circuit data to be arranged is to be written into the programmable device, in accordance with the determination result of the determination unit.