Patents by Inventor Haruji Yamazaki

Haruji Yamazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6389583
    Abstract: A semiconductor device has an N-channel output transistor N1 including a first gate electrode GP11A formed to surround contact holes C11 in a drain region of the output transistor for contacting a first wiring M11. An N-channel protective transistor N2 including a second gate electrode GP12A formed to surround contact holes C12 in a drain region for contacting a second wiring M12. The interval of the contact holes C11 is greater than the interval of contact holes C2 in a source region of each the transistors. By changing the number of the contact holes C11, C12 surrounded by the gate electrodes GP11A and GP12A, the size of each of the N-channel output transistor N1 and N-channel protective transistor N2 is changed.
    Type: Grant
    Filed: January 19, 2000
    Date of Patent: May 14, 2002
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Haruji Yamazaki
  • Patent number: 4212025
    Abstract: In a first conductivity type semiconductor substrate a plurality of second conductivity type regions are formed. First conductivity type resistivity regions are formed in the second conductivity type regions, respectively. The first conductivity type resistive regions are connected in series between power source terminals, through at least one divided potential taking-out electrode.
    Type: Grant
    Filed: January 31, 1978
    Date of Patent: July 8, 1980
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Masataka Hirasawa, Akira Hashimoto, Haruji Yamazaki