Patents by Inventor Haruka KUSAI
Haruka KUSAI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9768380Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes fin-type stacked layer structures. Each of the structures includes semiconductor layers stacked in a perpendicular direction. Assist gate electrodes are disposed in an in-plane direction and divided on a surface in the perpendicular direction of the structures.Type: GrantFiled: June 17, 2015Date of Patent: September 19, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kiwamu Sakuma, Masahiro Kiyotoshi, Atsuhiro Kinoshita, Haruka Kusai
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Publication number: 20150287913Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes fin-type stacked layer structures. Each of the structures includes semiconductor layers stacked in a perpendicular direction. Assist gate electrodes are disposed in an in-plane direction and divided on a surface in the perpendicular direction of the structures.Type: ApplicationFiled: June 17, 2015Publication date: October 8, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Kiwamu SAKUMA, Masahiro Kiyotoshi, Atsuhiro Kinoshita, Haruka Kusai
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Patent number: 9117848Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a fin structure stacked in order of a first oxide layer, a semiconductor layer and a second oxide layer in a first direction perpendicular to a surface of the semiconductor substrate, the fin structure extending in a second direction parallel to the surface of the semiconductor substrate, and a gate structure stacked in order of a gate oxide layer, a charge storage layer, a block insulating layer and a control gate electrode in a third direction perpendicular to the first and second directions from a surface of the semiconductor layer in the third direction.Type: GrantFiled: January 29, 2013Date of Patent: August 25, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Haruka Kusai, Kiwamu Sakuma, Masao Shingu, Shosuke Fujii, Masahiro Kiyotoshi
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Patent number: 9105838Abstract: According to one embodiment, a first electrode includes a metal element. A second electrode includes a semiconductor element. A third electrode includes a metal element. A first variable resistive layer is arranged between the first electrode and the second electrode and is capable of reversibly changing a resistance by filament formation and dissolution of the metal element of the first electrode. A second variable resistive layer is arranged between the second electrode and the third electrode and is capable of reversibly changing a resistance by filament formation and dissolution of the metal element of the third electrode.Type: GrantFiled: September 9, 2011Date of Patent: August 11, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Haimoto, Reika Ichihara, Haruka Kusai
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Patent number: 9087715Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure having memory cells, and a beam connected to an end portion of the structure. Each of the structure and the beam includes semiconductor layers stacked in a perpendicular direction. The beam includes a contact portion provided at one end of the beam, and a low resistance portion provided between the contact portion and the end portion of the structure.Type: GrantFiled: July 12, 2012Date of Patent: July 21, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Haruka Kusai, Kiwamu Sakuma, Shosuke Fujii, Masumi Saitoh, Masahiro Kiyotoshi
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Patent number: 9076722Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes fin-type stacked layer structures. Each of the structures includes semiconductor layers stacked in a perpendicular direction. Assist gate electrodes are disposed in an in-plane direction and divided on a surface in the perpendicular direction of the structures.Type: GrantFiled: July 12, 2012Date of Patent: July 7, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Kiwamu Sakuma, Masahiro Kiyotoshi, Atsuhiro Kinoshita, Haruka Kusai
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Patent number: 8994087Abstract: According to one embodiment, a semiconductor device includes a substrate and a first transistor. The substrate has a major surface. The first transistor is provided on the major surface. The first transistor includes a first stacked body, first and second conductive sections, a first gate electrode, and a first gate insulating film. The first stacked body includes first semiconductor layers and first insulating layers alternately stacked. The first semiconductor layers have a side surface. The first conductive section is electrically connected to one of the first semiconductor layers. The second conductive section is apart from the first conductive section and electrically connected to the one of the first semiconductor layers. The first gate electrode is provided between the first and second conductive sections and opposed to the side surface. The first gate insulating film is provided between the first gate electrode and the first semiconductor layers.Type: GrantFiled: January 10, 2013Date of Patent: March 31, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Masumi Saitoh, Toshinori Numata, Kiwamu Sakuma, Haruka Kusai
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Patent number: 8952441Abstract: According to one embodiment, a device includes a first fin structure having first to n-th semiconductor layers (n is a natural number equal to or more than 2) stacked in a first direction perpendicular to a surface of a semiconductor substrate, and extending in a second direction parallel to the surface of the semiconductor substrate, first to n-th memory cells provided on surfaces of the first to n-th semiconductor layers in a third direction perpendicular to the first and second directions respectively, and first to n-th select transistors connected in series to the first to n-th memory cells respectively.Type: GrantFiled: May 16, 2013Date of Patent: February 10, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Kiwamu Sakuma, Haruka Kusai, Yasuhito Yoshimizu, Masahiro Kiyotoshi
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Patent number: 8884648Abstract: One embodiment provides a programmable logic switch in which a first nonvolatile memory and a second nonvolatile memory are formed in the same well, and in which to change the first nonvolatile memory from an erased state to a written state and leave the second nonvolatile memory being in the erased state, a first write voltage is applied to a first line connected with gate electrodes of the first and second nonvolatile memories, a second write voltage is applied to a second line connected to a source in the first nonvolatile memory, and a third write voltage lower than the second write voltage is applied to a fourth line connected to a source of the second nonvolatile memory.Type: GrantFiled: April 4, 2013Date of Patent: November 11, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Koichiro Zaitsu, Kosuke Tatsumura, Mari Matsumoto, Shinichi Yasuda, Masato Oda, Haruka Kusai, Kiwamu Sakuma
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Patent number: 8710485Abstract: According to one embodiment, a semiconductor device includes a fin type stacked layer structure which has first to third semiconductor layers, and first to third layer select transistors to select one of the first to third semiconductor layers. The second layer select transistor is normally on in the second semiconductor layer, and is controlled to be on or off in the first and third semiconductor layers. A channel region of the second semiconductor layer which is covered with a gate electrode of the second layer select transistor has a metal silicide.Type: GrantFiled: April 27, 2012Date of Patent: April 29, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Masumi Saitoh, Toshinori Numata, Kiwamu Sakuma, Haruka Kusai, Takayuki Ishikawa
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Patent number: 8710580Abstract: According to one embodiment, a semiconductor device includes first to n-th semiconductor layers (n is a natural number equal to or more than 2) being stacked in order from a surface of an insulating layer in a first direction perpendicular to the surface of the insulating layer, the first to n-th semiconductor layers extending in a second direction parallel to the surface of the insulating layer, the first to n-th semiconductor layers being insulated from each other, a common electrode connected to the first to n-th semiconductor layers in a first end of the second direction thereof, and a layer select transistor which uses the first to n-th semiconductor layers as channels and which selects one of the first to n-th semiconductor layers.Type: GrantFiled: November 29, 2012Date of Patent: April 29, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kiwamu Sakuma, Haruka Kusai, Shosuke Fujii, Li Zhang, Masahiro Kiyotoshi, Masao Shingu
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Publication number: 20130307047Abstract: According to one embodiment, a device includes a first fin structure having first to n-th semiconductor layers (n is a natural number equal to or more than 2) stacked in a first direction perpendicular to a surface of a semiconductor substrate, and extending in a second direction parallel to the surface of the semiconductor substrate, first to n-th memory cells provided on surfaces of the first to n-th semiconductor layers in a third direction perpendicular to the first and second directions respectively, and first to n-th select transistors connected in series to the first to n-th memory cells respectively.Type: ApplicationFiled: May 16, 2013Publication date: November 21, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Kiwamu SAKUMA, Haruka KUSAI, Yasuhito YOSHIMIZU, Masahiro KIYOTOSHI
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Publication number: 20130181184Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes fin-type stacked layer structures. Each of the structures includes semiconductor layers stacked in a perpendicular direction. Assist gate electrodes are disposed in an in-plane direction and divided on a surface in the perpendicular direction of the structures.Type: ApplicationFiled: July 12, 2012Publication date: July 18, 2013Inventors: Kiwamu SAKUMA, Masahiro KIYOTOSHI, Atsuhiro KINOSHITA, Haruka KUSAI
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Publication number: 20130175490Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a fin-type stacked layer structure having memory cells, and a beam connected to an end portion of the structure. Each of the structure and the beam includes semiconductor layers stacked in a perpendicular direction. The beam includes a contact portion provided at one end of the beam, and a low resistance portion provided between the contact portion and the end portion of the structure.Type: ApplicationFiled: July 12, 2012Publication date: July 11, 2013Inventors: Haruka KUSAI, Kiwamu Sakuma, Shosuke Fujii, Masumi Saitoh, Masahiro Kiyotoshi
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Publication number: 20130134372Abstract: According to one embodiment, a semiconductor device includes first to n-th semiconductor layers (n is a natural number equal to or more than 2) being stacked in order from a surface of an insulating layer in a first direction perpendicular to the surface of the insulating layer, the first to n-th semiconductor layers extending in a second direction parallel to the surface of the insulating layer, the first to n-th semiconductor layers being insulated from each other, a common electrode connected to the first to n-th semiconductor layers in a first end of the second direction thereof, and a layer select transistor which uses the first to n-th semiconductor layers as channels and which selects one of the first to n-th semiconductor layers.Type: ApplicationFiled: November 29, 2012Publication date: May 30, 2013Inventors: Kiwamu SAKUMA, Haruka KUSAI, Shosuke FUJII, Li ZHANG, Masahiro KIYOTOSHI, Masao SHINGU
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Patent number: 8450709Abstract: According to one embodiment a first variable resistance layer which is arranged between a second electrode and a first electrode and in which a first conductive filament is capable of growing based on metal supplied from the second electrode, and an n-th variable resistance layer which is arranged between an n-th electrode and an (n+1)-th electrode and in which an n-th conductive filament whose growth rate is different from the first conductive filament is capable of growing based on metal supplied from the (n+1)-th electrode are included, a configuration in which a plurality of conductive filaments is electrically connected in series between the first electrode layer and the (n+1)-th electrode layer is included, and a resistance is changed in a stepwise manner.Type: GrantFiled: March 21, 2011Date of Patent: May 28, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Haruka Kusai, Shosuke Fujii, Yasushi Nakasaki
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Patent number: 8432186Abstract: One embodiment provides a programmable logic switch in which a first nonvolatile memory and a second nonvolatile memory are formed in the same well, and in which to change the first nonvolatile memory from an erased state to a written state and leave the second nonvolatile memory being in the erased state, a first write voltage is applied to a first line connected with gate electrodes of the first and second nonvolatile memories, a second write voltage is applied to a second line connected to a source in the first nonvolatile memory, and a third write voltage lower than the second write voltage is applied to a fourth line connected to a source of the second nonvolatile memory.Type: GrantFiled: May 31, 2012Date of Patent: April 30, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Koichiro Zaitsu, Kosuke Tatsumura, Mari Matsumoto, Shinichi Yasuda, Masato Oda, Haruka Kusai, Kiwamu Sakuma
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Publication number: 20120280303Abstract: According to one embodiment, a first trench extending in a first direction is formed in a stacked structure in which a plurality of spacer films and a plurality of channel semiconductor films are alternately stacked. A first space is formed by forming a recess in the channel semiconductor films from the first trench. A tunnel dielectric film is formed in the first space, and the first space is further filled with a floating gate electrode film. Second trenches that divide the stacked structure at predetermined interval in the first direction are formed so as to divide the floating gate electrode film between memory cells adjacent to each other in the first direction but not to divide the channel semiconductor films.Type: ApplicationFiled: February 6, 2012Publication date: November 8, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masahiro KIYOTOSHI, Kiwamu Sakuma, Haruka Kusai
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Publication number: 20120273747Abstract: According to one embodiment, a semiconductor device includes a fin type stacked layer structure which has first to third semiconductor layers, and first to third layer select transistors to select one of the first to third semiconductor layers. The second layer select transistor is normally on in the second semiconductor layer, and is controlled to be on or off in the first and third semiconductor layers. A channel region of the second semiconductor layer which is covered with a gate electrode of the second layer select transistor has a metal silicide.Type: ApplicationFiled: April 27, 2012Publication date: November 1, 2012Inventors: Masumi SAITOH, Toshinori NUMATA, Kiwamu SAKUMA, Haruka KUSAI, Takayuki ISHIKAWA
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Publication number: 20120211719Abstract: According to one embodiment, a first electrode includes a metal element. A second electrode includes a semiconductor element. A third electrode includes a metal element. A first variable resistive layer is arranged between the first electrode and the second electrode and is capable of reversibly changing a resistance by filament formation and dissolution of the metal element of the first electrode. A second variable resistive layer is arranged between the second electrode and the third electrode and is capable of reversibly changing a resistance by filament formation and dissolution of the metal element of the third electrode.Type: ApplicationFiled: September 9, 2011Publication date: August 23, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takashi HAIMOTO, Reika Ichihara, Haruka Kusai