Abstract: An accelerated test for applying a high voltage is performed without reducing a manufacturing yield of a semiconductor device using a wide gap semiconductor material. The technical idea in the embodiment is, for example, an idea of performing the accelerated test in the state of a semiconductor wafer to distinguish a latent defect as illustrated in FIG. 4. That is, the technical idea in the embodiment is to perform the accelerated test on a semiconductor chip containing a wide bandgap semiconductor material as a main component not in the state of a semiconductor chip but in the state of the semiconductor wafer.

Abstract: The present invention provides an exhaust gas purifying catalyst including a first catalyst layer (12). The first catalyst layer (12) includes a first section (14) and a second section (15) in an exhaust gas flow direction, the first section (14) being located on an upstream side in the exhaust gas flow direction relative to the second section (15). The first section (14) and the second section (15) both contain a catalytically active component including a specific element. A concentration of the specific element is higher in the first section (14) than in the second section (15). A concentration gradient of the specific element contained in the first section (14) in a thickness direction of the catalyst layer (12) is milder than a concentration gradient of the specific element contained in the second section (15) in the thickness direction.

Abstract: The present invention provides an exhaust gas purifying catalyst including a first catalyst layer (12). The first catalyst layer (12) includes a first section (14) and a second section (15) in an exhaust gas flow direction, the first section (14) being located on an upstream side in the exhaust gas flow direction relative to the second section (15). The first section (14) and the second section (15) both contain a catalytically active component including a specific element. A concentration of the specific element is higher in the first section (14) than in the second section (15). A concentration gradient of the specific element contained in the first section (14) in a thickness direction of the catalyst layer (12) is milder than a concentration gradient of the specific element contained in the second section (15) in the thickness direction.

Abstract: A privilege provision device according to an embodiment of the present invention includes a payment token request reception unit configured to receive a token request including user identification information from a user terminal, a token generation unit configured to generate a token associated with coupon identification information and the user identification information, a token transmission unit configured to transmit the token to the user terminal, a payment request reception unit configured to receive a payment request including the token from a store terminal, a validity determination unit configured to determine whether or not a coupon associated with the coupon identification information is valid at the time of the reception of the token request, and a privilege provision unit configured to provide the user with a privilege by the coupon associated with the coupon identification information corresponding to the token is in a case where the validity determination unit determines that the coupon is val

Abstract: An object of the present invention is to improve assemblability of a power semiconductor device. A power semiconductor device includes a plurality of submodules that includes a semiconductor element interposed between a source conductor and a drain conductor, a sense wiring that transmits a sense signal of the semiconductor element, and an insulating portion at which the sense wiring and the sense conductor are arranged, and a source outer conductor that is formed to surround the source conductor and is joined to the source conductor in each of the plurality of submodules. Each source conductor included in the plurality of submodules includes protrusion portions that are formed toward the sensor wiring from the source conductor, are connected to the sense wiring, and define a distance between the sense wiring and the source outer conductor.

Abstract: An object of the present invention is to improve assemblability of a power semiconductor device. A power semiconductor device includes a plurality of submodules that includes a semiconductor element interposed between a source conductor and a drain conductor, a sense wiring that transmits a sense signal of the semiconductor element, and an insulating portion at which the sense wiring and the sense conductor are arranged, and a source outer conductor that is formed to surround the source conductor and is joined to the source conductor in each of the plurality of submodules. Each source conductor included in the plurality of submodules includes protrusion portions that are formed toward the sensor wiring from the source conductor, are connected to the sense wiring, and define a distance between the sense wiring and the source outer conductor.

Abstract: Proposed is a phosphor capable of effectively inhibiting the occurrence of adverse influence of a sulfur-based gas while improving water resistance of the phosphor and effectively inhibiting the corrosion of a metallic member. A phosphor is proposed, which includes particles or a layer provided on the surface of a sulfur-containing phosphor, which contains sulfur in a host material, and containing a crystalline metal borate containing an IIA-Group element, boron, and oxygen.

Abstract: To solve a problem of realizing a large current and highly reliable power semiconductor device while shrinking a unit cell. A semiconductor device according to the present invention includes a plurality of p-type body regions extending in a first direction. The semiconductor device further includes: a JFET region formed to extend in the first direction between p-type body regions which are adjacent to each other in a second direction orthogonal to the first direction; an n+-type source region formed to extend in the first direction within a p-type body region and separate from an end side surface of the p-type body; and a channel region formed to extend in the first direction and in a top layer portion of a p-type body region between an end side surface of the p-type body region and an end side surface of an n+-type source region.

Abstract: To solve a problem of realizing a large current and highly reliable power semiconductor device while shrinking a unit cell. A semiconductor device according to the present invention includes a plurality of p-type body regions extending in a first direction. The semiconductor device further includes: a JFET region formed to extend in the first direction between p-type body regions which are adjacent to each other in a second direction orthogonal to the first direction; an n+-type source region formed to extend in the first direction within a p-type body region and separate from an end side surface of the p-type body; and a channel region formed to extend in the first direction and in a top layer portion of a p-type body region between an end side surface of the p-type body region and an end side surface of an n+-type source region.

Abstract: Proposed is a phosphor capable of effectively inhibiting the occurrence of adverse influence of a sulfur-based gas while improving water resistance of the phosphor and effectively inhibiting the corrosion of a metallic member. A phosphor is proposed, which includes particles or a layer provided on the surface of a sulfur-containing phosphor, which contains sulfur in a host material, and containing a crystalline metal borate containing an IIA-Group element, boron, and oxygen.

Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.

Abstract: A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n+-type source layer on a surface of an n?-type drift layer formed on an n+-type SiC substrate; (b) forming a plurality of shallow trenches disposed at predetermined intervals by etching the surface of the n?-type drift layer with a silicon oxide film formed on the n?-type drift layer used as a mask; (c) forming an n-type counter dope layer by doping the n?-type drift layer below each of the shallow trenches with nitrogen by using a vertical ion implantation method; (d) forming a sidewall spacer on each sidewall of the silicon oxide film and the shallow trenches; and (e) forming a p-type gate layer by doping the n?-type drift layer below each of shallow trenches with aluminum by using the vertical ion implantation method.

Abstract: Provided is a novel CaS-based phosphor with which chemical reactions can be inhibited even if said CaS-based phosphor is heated with a heterogeneous material. This phosphor includes: a crystalline parent material represented by the composition formula Ca1-xSrxS.yZnO (in the formula, 0?x<1, 0<y?0.5); and a luminescent center.

Abstract: A normally-off type silicon carbide junction FET has a problem that the gate thereof is not easy to use due to inferiority in the characteristics of it. This problem occurs because in order to achieve normally-off, the gate voltage should be off at 0V and at the same time, the ON-state gate voltage should be suppressed to about 2.5V to prevent the passage of an electric current through a pn junction between gate and source. Accordingly, a range from the threshold voltage to the ON-state gate voltage is only from about 1 V to 2V and it is difficult to control the gate voltage. Provided in the present invention is an electronic circuit device obtained by coupling, to a gate of a normally-off type silicon carbide junction FET, an element having a capacitance equal to or a little smaller than the gate capacitance of the junction FET.

Abstract: A highly reliable light-emitting device is provided, which is capable of effectively suppressing detrimental effects of sulfuric gas. A light-emitting device comprising a solid light-emitting element 1, a metal member 2 reacting with sulfuric gas and a phosphor-containing layer 5 that contains a phosphor 3, the phosphor-containing layer 5 containing a sulfuric gas-adsorbing substance 4 that adsorbs sulfuric gas, and, when the phosphor-containing layer 5 is tripartitioned from the side near the metal member to far into a proximal layer portion, an intermediate layer portion and an outer layer portion, the concentration of sulfuric gas-adsorbing substance 4 in the proximal layer portion is made to be higher than those for the intermediate layer portion and the outer layer portion.

Abstract: A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n+-type source layer on a surface of an n?-type drift layer formed on an n+-type SiC substrate; (b) forming a plurality of shallow trenches disposed at predetermined intervals by etching the surface of the n?-type drift layer with a silicon oxide film formed on the n?-type drift layer used as a mask; (c) forming an n-type counter dope layer by doping the n?-type drift layer below each of the shallow trenches with nitrogen by using a vertical ion implantation method; (d) forming a sidewall spacer on each sidewall of the silicon oxide film and the shallow trenches; and (e) forming a p-type gate layer by doping the n?-type drift layer below each of shallow trenches with aluminum by using the vertical ion implantation method.

Abstract: A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n+-type source layer on a surface of an n?-type drift layer formed on an n+-type SiC substrate; (b) forming a plurality of shallow trenches disposed at predetermined intervals by etching the surface of the n?-type drift layer with a silicon oxide film formed on the n?-type drift layer used as a mask; (c) forming an n-type counter dope layer by doping the n?-type drift layer below each of the shallow trenches with nitrogen by using a vertical ion implantation method; (d) forming a sidewall spacer on each sidewall of the silicon oxide film and the shallow trenches; and (e) forming a p-type gate layer by doping the n?-type drift layer below each of shallow trenches with aluminum by using the vertical ion implantation method.

Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.

Abstract: Provided is a novel CaS-based phosphor with which chemical reactions can be inhibited even if said CaS-based phosphor is heated with a heterogeneous material. This phosphor includes: a crystalline parent material represented by the composition formula Ca1-xSrxS.yZnO (in the formula, 0?x<1, 0<y?0.5); and a luminescent center.

Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.