Patents by Inventor Haruki Souma

Haruki Souma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method to seperate storage regions in the mirror bit device
    Patent number: 8318566
    Abstract: Devices and methods for isolating adjacent charge accumulation layers in a semiconductor device are disclosed. In one embodiment, a semiconductor device comprises a bit line formed in a semiconductor substrate, a charge accumulation layer formed on the semiconductor substrate, a word line formed on the charge accumulation layer across the bit line, and a channel region formed in the semiconductor substrate below the word line and between the bit line and its adjacent bit line. For the semiconductor device, the charge accumulation layer is formed above the channel region in a widthwise direction of the word line, and a width of the word line is set to be narrower than a distance between an end of the channel region and a central part of the channel region in a lengthwise direction of the word line.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: November 27, 2012
    Assignee: Spansion LLC
    Inventors: Fumihiko Inoue, Haruki Souma, Yukio Hayakawa
  • METHOD TO SEPERATE STORAGE REGIONS IN THE MIRROR BIT DEVICE
    Publication number: 20110233651
    Abstract: Devices and methods for isolating adjacent charge accumulation layers in a semiconductor device are disclosed. In one embodiment, a semiconductor device comprises a bit line formed in a semiconductor substrate, a charge accumulation layer formed on the semiconductor substrate, a word line formed on the charge accumulation layer across the bit line, and a channel region formed in the semiconductor substrate below the word line and between the bit line and its adjacent bit line. For the semiconductor device, the charge accumulation layer is formed above the channel region in a widthwise direction of the word line, and a width of the word line is set to be narrower than a distance between an end of the channel region and a central part of the channel region in a lengthwise direction of the word line.
    Type: Application
    Filed: June 8, 2011
    Publication date: September 29, 2011
    Inventors: Fumihiko INOUE, Haruki SOUMA, Yukio HAYAKAWA
  • Separation methods for semiconductor charge accumulation layers and structures thereof
    Patent number: 8003468
    Abstract: Devices and methods for isolating adjacent charge accumulation layers in a semiconductor device are disclosed. In one embodiment, a semiconductor device comprises a bit line formed in a semiconductor substrate, a charge accumulation layer formed on the semiconductor substrate, a word line formed on the charge accumulation layer across the bit line, and a channel region formed in the semiconductor substrate below the word line and between the bit line and its adjacent bit line. For the semiconductor device, the charge accumulation layer is formed above the channel region in a widthwise direction of the word line, and a width of the word line is set to be narrower than a distance between an end of the channel region and a central part of the channel region in a lengthwise direction of the word line.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: August 23, 2011
    Assignee: Spansion LLC
    Inventors: Fumihiko Inoue, Haruki Souma, Yukio Hayakawa
  • SEPERATION METHODS FOR SEMICONDUCTOR CHARGE ACCUMULATION LAYERS AND STRUCTURES THEREOF
    Publication number: 20090206388
    Abstract: Devices and methods for isolating adjacent charge accumulation layers in a semiconductor device are disclosed. In one embodiment, a semiconductor device comprises a bit line formed in a semiconductor substrate, a charge accumulation layer formed on the semiconductor substrate, a word line formed on the charge accumulation layer across the bit line, and a channel region formed in the semiconductor substrate below the word line and between the bit line and its adjacent bit line. For the semiconductor device, the charge accumulation layer is formed above the channel region in a widthwise direction of the word line, and a width of the word line is set to be narrower than a distance between an end of the channel region and a central part of the channel region in a lengthwise direction of the word line.
    Type: Application
    Filed: August 20, 2008
    Publication date: August 20, 2009
    Inventors: Fumihiko INOUE, Haruki SOUMA, Yukio HAYAKAWA