Patents by Inventor Haruki Yoneda
Haruki Yoneda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8525259Abstract: The invention prevents a source-drain breakdown voltage of a DMOS transistor from decreasing due to dielectric breakdown in a portion of a N type drift layer having high concentration formed in an active region near field oxide film corner portions surrounding an gate width end portion. The field oxide film corner portions are disposed on the outside of the gate width end portion so as to be further away from a P type body layer formed in the gate width end portion by forming the active region wider on the outside of the gate width end portion than in a gate width center portion. By this, the N type drift layer having high concentration near the field oxide film corner portions are disposed further away from the P type body layer without increasing the device area.Type: GrantFiled: May 25, 2010Date of Patent: September 3, 2013Assignees: Semiconductor Components Industries, LLC., SANYO Semiconductor Co., Ltd.Inventors: Yasuhiro Takeda, Kazunori Fujita, Haruki Yoneda
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Patent number: 8410557Abstract: A P type drift layer is formed in an N type epitaxial layer from under a drain layer to under an N type body layer under a source layer through under an element isolation insulation film. This P type drift layer is shallower immediately under the drain layer than under the element isolation insulation film, and gradually shallows from under the element isolation insulation film to the N type body layer to be in contact with the bottom of the N type body layer. Since the P type drift layer is thus diffused in a wide region, a wide current path is formed from the N type body layer to the drain layer, and the current drive ability is enhanced and the drain breakdown voltage is also increased.Type: GrantFiled: June 17, 2009Date of Patent: April 2, 2013Assignee: Semiconductor Components Industries, LLCInventors: Haruki Yoneda, Kazuhiro Sasada
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Patent number: 8115256Abstract: A semiconductor device includes an inverter having an NMOSFET and a PMOSFET having sources, drains and gate electrodes respectively, the drains being connected to each other and the gate electrodes being connected to each other, and a pnp bipolar transistor including a collector (C), a base (B) and an emitter (E), the base (B) receiving an output of the inverter.Type: GrantFiled: August 31, 2007Date of Patent: February 14, 2012Assignee: Sanyo Electric Co., Ltd.Inventors: Haruki Yoneda, Hideaki Fujiwara
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Patent number: 7968941Abstract: A semiconductor device includes: an epitaxial layer; a body layer, formed in the epitaxial layer, which includes a channel region; a source layer disposed in superposition on the body layer; a gate insulator, formed on the epitaxial layer, which is in a ring shape surrounding the source layer; a gate electrode formed through the gate insulator; a drift layer, formed in the epitaxial layer, which is in a ring shape surrounding the body layer; and a drain layer formed in the surface of the epitaxial layer and disposed opposite to the source layer. The body layer is disposed such that the boundary surface at an end in the gate-width direction is in contact with the undersurface of the gate insulator. The gate insulator has a thick film portion thicker than a part above the channel region in the gate-length direction at least in a part where the gate insulator is in contact with the boundary surface of the body layer at the end in the gate-width direction.Type: GrantFiled: March 27, 2009Date of Patent: June 28, 2011Assignee: Sanyo Electric Co., Ltd.Inventors: Kazunori Fujita, Tomio Yamashita, Haruki Yoneda, Kazuhiro Sasada
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Publication number: 20100301411Abstract: The invention prevents a source-drain breakdown voltage of a DMOS transistor from decreasing due to dielectric breakdown in a portion of a N type drift layer having high concentration formed in an active region near field oxide film corner portions surrounding an gate width end portion. The field oxide film corner portions are disposed on the outside of the gate width end portion so as to be further away from a P type body layer formed in the gate width end portion by forming the active region wider on the outside of the gate width end portion than in a gate width center portion. By this, the N type drift layer having high concentration near the field oxide film corner portions are disposed further away from the P type body layer without increasing the device area.Type: ApplicationFiled: May 25, 2010Publication date: December 2, 2010Applicants: SANYO Electric Co., Ltd.Inventors: Yasuhiro TAKEDA, Kazunori Fujita, Haruki Yoneda
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Patent number: 7649222Abstract: This semiconductor device includes a first conductivity type first semiconductor layer formed on the upper surface of a substrate, a first conductivity type second semiconductor layer formed on the first semiconductor layer, a first conductivity type third semiconductor layer formed on the second semiconductor layer, a second conductivity type fourth semiconductor layer formed on the third semiconductor layer, a first conductivity type fifth semiconductor layer formed on the fourth semiconductor layer and an electrode formed in a trench, so provided as to reach the second semiconductor layer through at least the fifth semiconductor layer, the fourth semiconductor layer and the third semiconductor layer, in contact with an insulating film, while the upper surface of the second semiconductor layer is arranged upward beyond the lower end of the electrode.Type: GrantFiled: December 21, 2007Date of Patent: January 19, 2010Assignee: Sanyo Electric Co., Ltd.Inventor: Haruki Yoneda
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Publication number: 20090321852Abstract: A P type drift layer is formed in an N type epitaxial layer from under a drain layer to under an N type body layer under a source layer through under an element isolation insulation film. This P type drift layer is shallower immediately under the drain layer than under the element isolation insulation film, and gradually shallows from under the element isolation insulation film to the N type body layer to be in contact with the bottom of the N type body layer. Since the P type drift layer is thus diffused in a wide region, a wide current path is formed from the N type body layer to the drain layer, and the current drive ability is enhanced and the drain breakdown voltage is also increased.Type: ApplicationFiled: June 17, 2009Publication date: December 31, 2009Applicant: SANYO Electric Co., Ltd.Inventors: Haruki YONEDA, Kazuhiro Sasada
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Patent number: 7638409Abstract: A highly reliable semiconductor device that controls both defects and impurity diffusion and a method for manufacturing such a semiconductor device. An N+ embedment layer and an N-type epitaxial layer are formed on a main surface region of a P-type silicon substrate. An STI trench is formed in the N-type epitaxial layer. A thermal oxidation film is formed on the inner surface of the STI trench. The STI trench is filled with an HDP-NSG film. A deep trench is formed in the STI trench with a depth reaching the silicon substrate. A further thermal oxidation film is formed on the inner surface of the deep trench. The thermal oxidation film of the deep trench is thinner than that of the STI trench. A silicon oxidation film is also formed in the deep trench and filled with a polysilicon film.Type: GrantFiled: February 19, 2008Date of Patent: December 29, 2009Assignee: Sanyo Electric Co., Ltd.Inventor: Haruki Yoneda
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Publication number: 20090242981Abstract: A semiconductor device includes: an epitaxial layer; a body layer, formed in the epitaxial layer, which includes a channel region; a source layer disposed in superposition on the body layer; a gate insulator, formed on the epitaxial layer, which is in a ring shape surrounding the source layer; a gate electrode formed through the gate insulator; a drift layer, formed in the epitaxial layer, which is in a ring shape surrounding the body layer; and a drain layer formed in the surface of the epitaxial layer and disposed opposite to the source layer. The body layer is disposed such that the boundary surface at an end in the gate-width direction is in contact with the undersurface of the gate insulator. The gate insulator has a thick film portion thicker than a part above the channel region in the gate-length direction at least in a part where the gate insulator is in contact with the boundary surface of the body layer at the end in the gate-width direction.Type: ApplicationFiled: March 27, 2009Publication date: October 1, 2009Applicant: SANYO Electric Co., Ltd.Inventors: Kazunori Fujita, Tomio Yamashita, Haruki Yoneda, Kazuhiro Sasada
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Publication number: 20080258231Abstract: A semiconductor device includes an inverter having an NMOSFET and a PMOSFET having sources, drains and gate electrodes respectively, the drains being connected to each other and the gate electrodes being connected to each other, and a pnp bipolar transistor including a collector (C), a base (B) and an emitter (E), the base (B) receiving an output of the inverter.Type: ApplicationFiled: August 31, 2007Publication date: October 23, 2008Applicant: Sanyo Electric Co., Ltd.Inventors: Haruki YONEDA, Hideaki Fujiwara
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Patent number: 7405461Abstract: A highly reliable semiconductor device that controls both defects and impurity diffusion and a method for manufacturing such a semiconductor device. An N+ embedment layer and an N-type epitaxial layer are formed on a main surface region of a P-type silicon substrate. An STI trench is formed in the N-type epitaxial layer. A thermal oxidation film is formed on the inner surface of the STI trench. The STI trench is filled with an HDP-NSG film. A deep trench is formed in the STI trench with a depth reaching the silicon substrate. A further thermal oxidation film is formed on the inner surface of the deep trench. The thermal oxidation film of the deep trench is thinner than that of the STI trench. A silicon oxidation film is also formed in the deep trench and filled with a polysilicon film.Type: GrantFiled: September 7, 2005Date of Patent: July 29, 2008Assignee: Sanyo Electric Co., Ltd.Inventor: Haruki Yoneda
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Publication number: 20080150017Abstract: This semiconductor device includes a first conductivity type first semiconductor layer formed on the upper surface of a substrate, a first conductivity type second semiconductor layer formed on the first semiconductor layer, a first conductivity type third semiconductor layer formed on the second semiconductor layer, a second conductivity type fourth semiconductor layer formed on the third semiconductor layer, a first conductivity type fifth semiconductor layer formed on the fourth semiconductor layer and an electrode formed in a trench, so provided as to reach the second semiconductor layer through at least the fifth semiconductor layer, the fourth semiconductor layer and the third semiconductor layer, in contact with an insulating film, while the upper surface of the second semiconductor layer is arranged upward beyond the lower end of the electrode.Type: ApplicationFiled: December 21, 2007Publication date: June 26, 2008Applicant: SANYO ELECTRIC CO., LTD.Inventor: Haruki Yoneda
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Publication number: 20080153254Abstract: A highly reliable semiconductor device that controls both defects and impurity diffusion and a method for manufacturing such a semiconductor device. An N+ embedment layer and an N-type epitaxial layer are formed on a main surface region of a P-type silicon substrate. An STI trench is formed in the N-type epitaxial layer. A thermal oxidation film is formed on the inner surface of the STI trench. The STI trench is filled with an HDP-NSG film. A deep trench is formed in the STI trench with a depth reaching the silicon substrate. A further thermal oxidation film is formed on the inner surface of the deep trench. The thermal oxidation film of the deep trench is thinner than that of the STI trench. A silicon oxidation film is also formed in the deep trench and filled with a polysilicon film.Type: ApplicationFiled: February 19, 2008Publication date: June 26, 2008Applicant: SANYO ELECTRIC CO., LTD.Inventor: Haruki Yoneda
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Patent number: 7103284Abstract: A light-emitting module according to the present invention contains a Peltier element driver, and a signal processor for controlling the Peltier element driver. The Peltier element driver is mounted on a first substrate, which directly attaches to the inner bottom surface of the housing, while the signal processor is mounted on the other substrate spaced to the first substrate. The first substrate and the other substrate are vertically integrated within the housing. This arrangement enables to encase the Peltier element driver and the signal processor in the housing with effective thermal dissipation.Type: GrantFiled: September 26, 2002Date of Patent: September 5, 2006Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hirotaka Oomori, Haruki Yoneda, Shigeo Hayashi
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Publication number: 20060051932Abstract: A highly reliable semiconductor device that controls both defects and impurity diffusion and a method for manufacturing such a semiconductor device. An N+ embedment layer and an N-type epitaxial layer are formed on a main surface region of a P-type silicon substrate. An STI trench is formed in the N-type epitaxial layer. A thermal oxidation film is formed on the inner surface of the STI trench. The STI trench is filled with an HDP-NSG film. A deep trench is formed in the STI trench with a depth reaching the silicon substrate. A further thermal oxidation film is formed on the inner surface of the deep trench. The thermal oxidation film of the deep trench is thinner than that of the STI trench. A silicon oxidation film is also formed in the deep trench and filled with a polysilicon film.Type: ApplicationFiled: September 7, 2005Publication date: March 9, 2006Inventor: Haruki Yoneda
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Publication number: 20040008986Abstract: An optical transmitter apparatus includes a plurality of optical transmitter modules and a host controller. A module controller in each module determines whether the modulation current of a laser diode in the module is an anomaly, and also determines whether the temperature of the laser diode is an anomaly. If the modulation current or the temperature of the laser diode has an abnormal value, the module controller generates and sends an alarm signal from an alarm-outputting terminal. The alarm-outputting terminals of the modules are connected to an alarm-receiving terminal of the host controller in a wired-OR connection.Type: ApplicationFiled: May 8, 2003Publication date: January 15, 2004Inventors: Haruki Yoneda, Hirotaka Oomori, Shigeo Hayashi
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Publication number: 20030081289Abstract: A light-emitting module according to the present invention contains a Peltier element driver, and a signal processor for controlling the Peltier element driver. The Peltier element driver is mounted on a first substrate, which directly attaches to the inner bottom surface of the housing, while the signal processor is mounted on the other substrate spaced to the first substrate. The first substrate and the other substrate are vertically integrated within the housing. This arrangement enables to encase the Peltier element driver and the signal processor in the housing with effective thermal dissipation.Type: ApplicationFiled: September 26, 2002Publication date: May 1, 2003Inventors: Hirotaka Oomori, Haruki Yoneda, Shigeo Hayashi