Abstract: A high-voltage MOS transistor wherein a dopant concentration of a source offset region is set lower than a dopant concentration of a drain offset region whereby a resistance value of the resource region is set independently of a resistance value of the drain region in such a manner as to maintain a high sustaining breakdown voltage of the high-voltage MOS transistor, which is based on a voltage of the source offset region and a voltage of a substrate region directly under a gate insulating film during operation of the high-voltage MOS transistor.

Abstract: A system for updating an inactive system memory includes a first package set in an active state and having a first processor and a second package set in an inactive state and having a second processor. The first package includes a first buffer memory, a first write control unit for outputting a write control signal and an address signal to the first buffer memory in accordance with a write control signal output from the first processor to the first memory, and a first holding unit for holding update data and an address signal output from the first processor to the first memory, and outputting held contents as data of the first buffer memory in accordance with a write control signal output from the first write control unit to the first buffer memory. The second package has the same arrangement as the first package. The second processor in an inactive state updates the second memory in accordance with update data and address data set for the first memory and stored in the first buffer memory.

Abstract: A system for updating an inactive system memory includes a first package set in an active state and having a first processor and a second package set in an inactive state and having a second processor. The first package includes a first buffer memory, a first write control unit for outputting a write control signal and an address signal to the first buffer memory in accordance with a write control signal output from the first processor to the first memory, and a first holding unit for holding update data and an address signal output from the first processor to the first memory, and outputting held contents as data of the first buffer memory in accordance with a write control signal output from the first write control unit to the first buffer memory. The second package has the same arrangement as the first package. The second processor in an inactive state updates the second memory in accordance with update data and address data set for the first memory and stored in the first buffer memory.