Abstract: A heat sink 109 is configured by a plate component having a combined structure composed of a recess and a projection formed thereon, wherein the recess is formed by allowing a part of the plate component to be set back from the surface level of the residual region, and the projection is formed on one surface of the plate component with the progress of formation of the recess, so as to be built up above the level of the residual region of the one surface.

Abstract: A heat sink 109 is configured by a plate component having a combined structure composed of a recess and a projection formed thereon, wherein the recess is formed by allowing a part of the plate component to be set back from the surface level of the residual region, and the projection is formed on one surface of the plate component with the progress of formation of the recess, so as to be built up above the level of the residual region of the one surface.

Abstract: With a conventional semiconductor device, there occurs deterioration in adhesion strength of bonded parts between a lid and a substrate. A semiconductor device according to an embodiment of the invention includes a substrate, a semiconductor chip with one of surfaces thereof, facing downward, mounted on the substrate, and a lid having a depressed part for accommodating the semiconductor chip, and a flange linked with the depressed part. Parts of the flange of the lid are bonded to the substrate by means of a binder. The flange is warped arcuately against the substrate, as seen in a side view. The bottom surface of the depressed part of the lid is bonded to the other surface of the semiconductor chip by means of a binder.

Abstract: A packaged semiconductor device comprises a packaging substrate having a core substrate having core wiring layers formed on opposite surfaces thereof, respectively, and a plurality of core via holes in the core substrate for mutually electrically connecting the core wiring layers formed on the opposite surfaces of the core substrate. Upper and lower buildup layers, each having a wiring layer, are formed on an upper surface and a lower surface of the core substrate, respectively. A semiconductor device chip is mounted on mounting pads formed on the upper buildup layer, and externally connecting electrodes are formed on the lower buildup layer. The position of the core via holes in the core substrate is standardized, regardless of the size of semiconductor device chip to be mounted. When a semiconductor device chip having a different chip size, the mounting pads formed on the upper buildup layer are located to coincide connection terminals of the semiconductor device chip of the different kind to be mounted.

Abstract: A semiconductor device including: a circuit board having a plurality of first electrodes thereon: a semiconductor chip having a plurality of second electrodes thereon: a bonding sheet sandwiched between said circuit boar and said semiconductor chip and having a plurality of apertures; and a solder bump disposed in each of apertures for connecting a corresponding one of the first electrodes and a corresponding one of the second electrodes. The semiconductor device can be manufactured without a conventional resin-applying step, thereby removing the cost for conducting the step. Also a short-circuit failure can be effectively prevented because the solder bumps are securely maintained in the apertures.

Abstract: A packaged semiconductor device comprises a packaging substrate having a core substrate having core wiring layers formed on opposite surfaces thereof, respectively, and a plurality of core via holes in the core substrate for mutually electrically connecting the core wiring layers formed on the opposite surfaces of the core substrate. Upper and lower buildup layers, each having a wiring layer, are formed on an upper surface and a lower surface of the core substrate, respectively. A semiconductor device chip is mounted on mounting pads formed on the upper buildup layer, and externally connecting electrodes are formed on the lower buildup layer. The position of the core via holes in the core substrate is standardized, regardless of the size of semiconductor device chip to be mounted. When a semiconductor device chip having a different chip size, the mounting pads formed on the upper buildup layer are located to coincide connection terminals of the semiconductor device chip of the different kind to be mounted.

Abstract: A multilayer printed circuit board has a substrate, an inner interconnection layer formed on each surface of the substrate, and an outer interconnection layer overlying each inner interconnection layer. The inner interconnection layer is formed of a copper sheet and two latticed metal films made of a metal having a low thermal expansion coefficient and bonded to boty surfaces of the copper sheet under application of pressure. The area ratio of exposed portions of the copper sheet to the whole surface of the interconnection layer is between 25 and 75%. Thermal expansion coefficient of the resultant circuit board is lowered to be close to the thermal expansion coefficient of a LSI, thereby obtaining reliability of a electronic product due to a low thermal stress. The metallic film is made of Kovar or Invar.