Abstract: An object is to effectively take measures against erroneous measurement of distance measurement information based on a laser light source. Therefore, a semiconductor device according to the present technology includes an imaging unit including a photoelectric conversion element that receives reflected light of light emitted from a specific laser light source reflected by a subject and performs photoelectric conversion and a control unit that executes validity determination processing for determining whether or not the light received by the photoelectric conversion element is the light emitted from the specific laser light source.

Abstract: The present technology relates to a semiconductor apparatus and electronic equipment that are configured to make it possible to take measures more effectively against malfunctions arising from electromagnetic waves. A semiconductor apparatus includes a first base that transmits at least part of an electromagnetic wave, a first transistor group related to to-be-protected information, and an electromagnetic-wave attenuating unit that is provided in at least part of a region between the first base and the first transistor group and attenuates the electromagnetic wave. The present technology can be applied to a solid-state image pickup apparatus and the like, for example.

Abstract: There is provided an encryption device that is secure against a side channel attack, and can suppress a processing load. The encryption device includes a data encryption part in which at least part of a plurality of round functions for successively performing encryption processing on an input value is tabulated to be encrypted using a white-box model in which input/output values of the round function is able to be recognized from the outside. Each of the round functions includes a tabulated encryption function for encrypting an input value using a black-box model in which the input/output values are able to be recognized from the outside and an intermediate value is not able to be recognized from the outside, and the encryption function is updated with a random number.

Abstract: There is provided an encryption device to suppress calculation in the reverse direction in whitebox model encryption. The encryption device includes: having a predetermined relationship that outputs a plurality of output values according to a plurality of input values configured of plain text, with a part of the plurality of output values being inputted to a trapdoor one-way function, the predetermined relationship being defined by the output values that are not inputted to the trapdoor one-way function and one arbitrary input value of the plurality of input values; and having a property of encrypting a part of the plurality of output values according to the trapdoor one-way function, and the trapdoor one-way function not being able to decrypt encrypted data in a state in which a trapdoor is unknown.

Abstract: There is provided an encryption device that is secure against a side channel attack, and can suppress a processing load. The encryption device includes a data encryption part in which at least part of a plurality of round functions for successively performing encryption processing on an input value is tabulated to be encrypted using a white-box model in which input/output values of the round function is able to be recognized from the outside. Each of the round functions includes a tabulated encryption function for encrypting an input value using a black-box model in which the input/output values are able to be recognized from the outside and an intermediate value is not able to be recognized from the outside, and the encryption function is updated with a random number.

Abstract: There is provided an encryption device to suppress calculation in the reverse direction in whitebox model encryption. The encryption device includes: having a predetermined relationship that outputs a plurality of output values according to a plurality of input values configured of plain text, with a part of the plurality of output values being inputted to a trapdoor one-way function, the predetermined relationship being defined by the output values that are not inputted to the trapdoor one-way function and one arbitrary input value of the plurality of input values; and having a property of encrypting a part of the plurality of output values according to the trapdoor one-way function, and the trapdoor one-way function not being able to decrypt encrypted data in a state in which a trapdoor is unknown.

Abstract: Provided an information processing apparatus including a number generation unit configured to generate numbers used in coefficients of terms included in a pair of multi-order multivariate polynomials F=(f1, . . . , fm), using a predetermined function, from information shared between entities executing an algorithm of a public-key authentication scheme or a digital signature scheme that uses a public key including the pair of multi-order multivariate polynomials F, and an allocation unit configured to allocate the numbers generated by the number generation unit to the coefficients of the multi-order multivariate polynomials for which the pair of multi-order multivariate polynomials F are included in constituent elements.

Abstract: There is provided an information processing apparatus including a key selection section configured to select one out of a plurality of different secret keys, in a public key authentication scheme or a digital signature scheme in which each of the plurality of secret keys exists for one public key registered in a verifier, and a process execution section configured to execute, by using the secret key selected by the key selection section, an authentication process with the verifier by the public key authentication scheme or a digital signature generation process to the verifier by the digital signature scheme.

Abstract: Provided is an arithmetic operation device including a plurality of shift registers each constituted by first to (N+1)th registers and a control unit configured to cause the shift registers to move stored values. The control unit causes the stored values to be output from a predetermined pair of registers constituting the first shift register while causing the stored values to move so that all combinations of a pair of stored values selectable from the stored values are output, and causes the stored values to be output from a predetermined pair of registers constituting the other shift register while causing the stored values to move.

Abstract: An authentication device includes circuitry that holds L (L?2) secret keys si (i=1 to L) and L public keys yi that satisfy yi=F(si) with respect to a set F of multivariate polynomials of n-th order (n?2). The circuitry also performs with a verifier, an interactive protocol for proving knowledge of (L?1) secret keys si that satisfy yi=F(si). The circuitry receives L challenges from the verifier, arbitrarily selects (L?1) challenges from the L challenges received. The circuitry also generates, by using the secret keys si, (L?1) responses respectively for the (L?1) challenges selected, and transmits the (L?1) responses generated.

Abstract: An information processing apparatus including a memory and one or more processors coupled to the memory and configured to transmit commitment information, including identification information of a verification processing apparatus, to the verification processing apparatus, receive first challenge information from the verification processing apparatus, generate second challenge information including the identification information based on the received first challenge information, generate response information, used for the verification processing apparatus to execute a process related to verification of the information processing apparatus, based on the generated second challenge information, and transmit the response information to the verification processing apparatus.

Abstract: Included is an encryption processing unit configured to divide and input configuration bits of data to be data processed into a plurality of lines, and to repeatedly execute data conversion processing of data for each line. The encryption processing unit includes an F function execution unit to input data from one line configuring the plurality of lines and generate converted data, an XOR calculation unit to execute an XOR calculation with other lines of data corresponding to the output from the F function, an intermediate data storage register to store intermediate data during the process of generating converted data in the F function execution unit, and an inverse calculation executing unit to calculate input data regarding the F function execution unit on the basis of the data stored in the intermediate storage register.

Abstract: An information processing apparatus including a random number generation unit configured to generate a pair of random numbers from a seed, a message generation unit configured to generate a message based on a pair of multi-order multivariate polynomials F=(f1, . . . , fm) defined in a ring K, the pair of random numbers, and a vector s that is an element of a set Kn, a message supply unit configured to supply the message to a verifier storing the pair of multi-order multivariate polynomials F and vectors y=(y1, . . . , ym)=(f1(s), . . . , fm(s)), and a response supply unit configured to supply the verifier with response information corresponding to a verification pattern selected by the verifier from among k (where k?3) verification patterns.

Abstract: An encryption processing device including an encryption processing part configured to divide configuration bits of data to be data processed into plural lines, and to input, and to repeatedly execute data conversion processing applying a round function to each line of data as a round calculation; and a key scheduling part configured to output round keys to a round calculation executing unit in the encryption processing part. The key scheduling part is a replacement type key scheduling part configured to generate plural round keys or round key configuration data by dividing a secret key stored beforehand into plural parts. The plural round keys are output to a round calculation executing unit sequentially executing in the encryption processing part such that a constant sequence is not repeated. The encryption processing configuration has a high level of security and a high level of resistance to repeated key attacks or other attacks.

Abstract: An authentication device includes circuitry that holds L (L?2) secret keys si (i=1 to L) and L public keys yi that satisfy yi=F(si) with respect to a set F of multivariate polynomials of n-th order (n?2). The circuitry also performs with a verifier, an interactive protocol for proving knowledge of (L?1) secret keys si that satisfy yi=F(si). The circuitry receives L challenges from the verifier, arbitrarily selects (L?1) challenges from the L challenges received. The circuitry also generates, by using the secret keys si, (L?1) responses respectively for the (L?1) challenges selected, and transmits the (L?1) responses generated.

Abstract: A signature verification apparatus including a signature acquisition unit configured to acquire a digital signature including first information generated based on a pair of multi-order multivariate polynomials F=(f1, . . . , fm) defined in a ring K, a signature key s which is an element of a set Kn, and a document M and a plurality of pieces of second information for verifying that the first information is generated using the signature key s based on the data M, the pair of multi-order multivariate polynomials F, and vectors y=(f1(s), . . . , fm(s)), and a signature verification unit configured to verify legitimacy of the document M by confirming whether or not the first information is restorable using the plurality of pieces of second information included in the digital signature. The pair of multivariate polynomials F and the vectors y are public keys.

Abstract: There is provided a print medium, whereon a public key used for authentication in a public-key authentication scheme is displayed as character information.

Abstract: A miniaturized non-linear conversion unit is achieved. Included is an encryption processing part configured to divide and input configuration bits of data to be processed into a plurality of lines, and to repeatedly execute a data conversion processing applying a round function as to the data in each line, wherein the encryption processing part includes an F function executing unit configured to input one line of data configuring the plurality of lines, and to generate conversion data, wherein the F function executing unit includes a non-linear conversion processing unit configured to execute a non-linear conversion processing, and wherein the non-linear conversion processing unit includes a repeating structure of a non-linear calculation unit made up from either one NAND or NOR, and either one XOR or XNOR calculation unit, and a bit replacement unit. The miniaturized non-linear conversion unit is achieved by this repeating configuration.

Abstract: An authentication device includes circuitry that holds L (L?2) secret keys si (i=1 to L) and L public keys yi that satisfy yi=F(si) with respect to a set F of multivariate polynomials of n-th order (n?2). The circuitry also performs with a verifier, an interactive protocol for proving knowledge of (L?1) secret keys si that satisfy yi=F(si). The circuitry receives L challenges from the verifier, arbitrarily selects (L?1) challenges from the L challenges received. The circuitry also generates, by using the secret keys si, (L?1) responses respectively for the (L?1) challenges selected, and transmits the (L?1) responses generated.

Abstract: A reduction in the size of encryption processing configuration applying generalized Feistel structures is achieved. The encryption processing configuration applies a generalized Feistel structure for dividing and inputting data into multiple lines, and repeatedly executing data transformation processing applying a round function on the data transferred to each line, and during the execution cycle of a matrix operation by a matrix operation executing unit for executing linear transformation processing applying a matrix on the data in a first line, an operation is executed on the matrix operation processing data from the initial cycle and data in a second line. This configuration enables a register to be used for both the storage of the data for the second line and the storage of the results of the matrix operation on the first line of data in progress, a reduction in the total number of registers, and thus a reduction in size.