Patents by Inventor Harunaka Yamaguchi
Harunaka Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230327040Abstract: A buffer layer (2), a multiplication layer (3), a light-absorbing layer (5), a window layer (6,7), and a contact layer (8) are sequentially stacked on a semiconductor substrate (1). The window layer (6,7) is doped with an impurity to form a p-type region (9). A bandgap of the window layer (6,7) is greater than a bandgap of the light-absorbing layer (5). The window layer (6,7) includes a first window layer (6), and a second window layer (7) formed on the first window layer (1). A diffusion rate of the impurity in the second window layer (7) is higher than a diffusion rate of the impurity in the first window layer (6). The first window layer (6) is a Ru, Rh or Os-doped InP layer.Type: ApplicationFiled: January 21, 2021Publication date: October 12, 2023Applicant: Mitsubishi Electric CorporationInventor: Harunaka YAMAGUCHI
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Patent number: 11329179Abstract: A multiplication layer on a semiconductor substrate of n-type contains Al atoms. An electric field control layer on the multiplication layer is of p-type, and includes a high-concentration area, and a low-concentration area lower in impurity concentration than the high-concentration area which is formed outside the high-concentration area. An optical absorption layer on the electric field control layer is lower in impurity concentration than the high-concentration area. A window layer of n-type formed on the optical absorption layer is larger in band gap than the optical absorption layer. A light-receiving area of p-type is formed apart from an outer edge of the window layer, and at least partly faces the high-concentration area through the window layer and the optical absorption layer. The guard ring area of p-type which the window layer separates from the light-receiving area penetrates through the window layer to extend into the optical absorption layer.Type: GrantFiled: September 15, 2017Date of Patent: May 10, 2022Assignee: Mitsubishi Electric CorporationInventors: Ryota Takemura, Eitaro Ishimura, Harunaka Yamaguchi
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Patent number: 10910222Abstract: An upper layer (4,5) made of non-doped III-V compound semiconductor is formed on a lower layer (3) made of non-doped III-V compound semiconductor. Impurity source gas is fed through vapor phase diffusion using an organometallic vapor-phase epitaxy device to add an impurity to the upper layer (4,5). The vapor phase diffusion is continued with the feed of the impurity source gas stopped or with a feed amount of the impurity source gas lowered.Type: GrantFiled: May 12, 2017Date of Patent: February 2, 2021Assignee: Mitsubishi Electric CorporationInventors: Eiji Nakai, Harunaka Yamaguchi
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Publication number: 20200357642Abstract: An upper layer (4,5) made of non-doped III-V compound semiconductor is formed on a lower layer (3) made of non-doped III-V compound semiconductor. Impurity source gas is fed through vapor phase diffusion using an organometallic vapor-phase epitaxy device to add an impurity to the upper layer (4,5). The vapor phase diffusion is continued with the feed of the impurity source gas stopped or with a feed amount of the impurity source gas lowered.Type: ApplicationFiled: May 12, 2017Publication date: November 12, 2020Applicant: Mitsubishi Electric CorporationInventors: Eiji NAKAI, Harunaka YAMAGUCHI
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Publication number: 20200203544Abstract: A multiplication layer on a semiconductor substrate of n-type contains Al atoms. An electric field control layer on the multiplication layer is of p-type, and includes a high-concentration area, and a low-concentration area lower in impurity concentration than the high-concentration area which is formed outside the high-concentration area. An optical absorption layer on the electric field control layer is lower in impurity concentration than the high-concentration area. A window layer of n-type formed on the optical absorption layer is larger in band gap than the optical absorption layer. A light-receiving area of p-type is formed apart from an outer edge of the window layer, and at least partly faces the high-concentration area through the window layer and the optical absorption layer. The guard ring area of p-type which the window layer separates from the light-receiving area penetrates through the window layer to extend into the optical absorption layer.Type: ApplicationFiled: September 15, 2017Publication date: June 25, 2020Applicant: Mitsubishi Electric CorporationInventors: Ryota TAKEMURA, Eitaro ISHIMURA, Harunaka YAMAGUCHI
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Patent number: 10079324Abstract: A semiconductor light-receiving device includes: a semi-insulating substrate; and a buffer layer, a p-type contact layer, a light absorption layer, a p-type field alleviating layer, an avalanche multiplication layer, an n-type field alleviating layer and an n-type contact layer laminated in order on the semi-insulating substrate, wherein the buffer layer includes a superlattice obtained by alternately laminating an InP layer and an AlxGayIn1-x-yAs layer (0.16?x?0.48, 0?y?0.31) and does not absorb light of a wavelength band absorbed by the light absorption layer.Type: GrantFiled: February 26, 2016Date of Patent: September 18, 2018Assignee: Mitsubishi Electric CorporationInventor: Harunaka Yamaguchi
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Patent number: 9948064Abstract: A method of manufacturing a semiconductor device includes a step of forming a mesa portion including an active layer above a substrate, and an n-type layer above the active layer, a step of forming a current confinement portion on left and right of the mesa portion, the current confinement portion including a p-type current blocking layer, an n-type current blocking layer above the p-type current blocking layer, and an i-type or p-type current blocking layer above the n-type current blocking layer, and a p-type doping step of diffusing p-type impurities into the i-type or p-type current blocking layer, an upper portion of the n-type current blocking layer, and left and right portions of the n-type layer to change the upper portion of the n-type current blocking layer and the left and right portions of the n-type layer to p-type semiconductors.Type: GrantFiled: January 12, 2017Date of Patent: April 17, 2018Assignee: Mitsubishi Electric CorporationInventors: Hiroaki Tsuchiya, Harunaka Yamaguchi, Eiji Nakai
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Publication number: 20170365981Abstract: A method of manufacturing a semiconductor device includes a step of forming a mesa portion including an active layer above a substrate, and an n-type layer above the active layer, a step of forming a current confinement portion on left and right of the mesa portion, the current confinement portion including a p-type current blocking layer, an n-type current blocking layer above the p-type current blocking layer, and an i-type or p-type current blocking layer above the n-type current blocking layer, and a p-type doping step of diffusing p-type impurities into the i-type or p-type current blocking layer, an upper portion of the n-type current blocking layer, and left and right portions of the n-type layer to change the upper portion of the n-type current blocking layer and the left and right portions of the n-type layer to p-type semiconductors.Type: ApplicationFiled: January 12, 2017Publication date: December 21, 2017Applicant: Mitsubishi Electric CorporationInventors: Hiroaki TSUCHIYA, Harunaka YAMAGUCHI, Eiji NAKAI
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Patent number: 9564525Abstract: A compound semiconductor device includes: a substrate; and a buffer layer, a first carrier supply layer, a first spacer layer, a channel layer, a second spacer layer, a second carrier supply layer, and a contact layer provided in order on the substrate, wherein the first carrier supply layer is a uniformly doped layer in which an impurity is uniformly doped, the second carrier supply layer is a planar doped layer in which an impurity is locally doped, and no Al mixed crystal layer having higher resistance values than the first and second spacer layers is provided between the buffer layer and the first spacer layer and between the second spacer layer and the contact layer.Type: GrantFiled: January 7, 2016Date of Patent: February 7, 2017Assignee: Mitsubishi Electric CorporationInventors: Susumu Hatakenaka, Harunaka Yamaguchi
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Publication number: 20170033254Abstract: A semiconductor light-receiving device includes: a semi-insulating substrate; and a buffer layer, a p-type contact layer, a light absorption layer, a p-type field alleviating layer, an avalanche multiplication layer, an n-type field alleviating layer and an n-type contact layer laminated in order on the semi-insulating substrate, wherein the buffer layer includes a superlattice obtained by alternately laminating an InP layer and an AlxGayIn1-x-yAs layer (0.16?x?0.48, 0?y?0.31) and does not absorb light of a wavelength band absorbed by the light absorption layer.Type: ApplicationFiled: February 26, 2016Publication date: February 2, 2017Applicant: Mitsubishi Electric CorporationInventor: Harunaka YAMAGUCHI
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Patent number: 9520526Abstract: A manufacturing method of an avalanche photodiode includes: forming a p-type field relaxation layer on a substrate; forming a cap layer on the p-type field relaxation layer; and forming a light absorbing layer on the cap layer, wherein a carbon is doped in the p-type field relaxation layer as a p-type dopant, the p-type field relaxation layer contains Al in a crystal composition, and a temperature-rise process from a growth temperature of the cap layer to a growth temperature of the light absorbing layer is performed in an inactive gas atmosphere without introducing a group V raw material.Type: GrantFiled: August 19, 2015Date of Patent: December 13, 2016Assignee: Mitsubishi Electric CorporationInventors: Harunaka Yamaguchi, Susumu Hatakenaka
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Publication number: 20160336438Abstract: A compound semiconductor device includes: a substrate; and a buffer layer, a first carrier supply layer, a first spacer layer, a channel layer, a second spacer layer, a second carrier supply layer, and a contact layer provided in order on the substrate, wherein the first carrier supply layer is a uniformly doped layer in which an impurity is uniformly doped, the second carrier supply layer is a planar doped layer in which an impurity is locally doped, and no Al mixed crystal layer having higher resistance values than the first and second spacer layers is provided between the buffer layer and the first spacer layer and between the second spacer layer and the contact layer.Type: ApplicationFiled: January 7, 2016Publication date: November 17, 2016Applicant: Mitsubishi Electric CorporationInventors: Susumu HATAKENAKA, Harunaka YAMAGUCHI
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Publication number: 20160155888Abstract: A manufacturing method of an avalanche photodiode includes: forming a p-type field relaxation layer on a substrate; forming a cap layer on the p-type field relaxation layer; and forming a light absorbing layer on the cap layer, wherein a carbon is doped in the p-type field relaxation layer as a p-type dopant, the p-type field relaxation layer contains Al in a crystal composition, and a temperature-rise process from a growth temperature of the cap layer to a growth temperature of the light absorbing layer is performed in an inactive gas atmosphere without introducing a group V raw material.Type: ApplicationFiled: August 19, 2015Publication date: June 2, 2016Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Harunaka YAMAGUCHI, Susumu HATAKENAKA
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Publication number: 20150214307Abstract: A method for manufacturing a semiconductor device includes: forming a buffer layer on a substrate; and sequentially forming an undoped multiplication layer, an electric field alleviating layer, a light absorption layer, and a window layer on the buffer layer, in that order, for forming an avalanche photodiode. Carbon is incorporated into the electric field alleviating layer as a p-type dopant, and a dopant impurity producing n-type conductivity and carbon are incorporated into the buffer layer.Type: ApplicationFiled: October 7, 2014Publication date: July 30, 2015Inventor: Harunaka Yamaguchi
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Publication number: 20140131827Abstract: An i-type AlInAs avalanche multiplication layer is grown on an n-type InP substrate. A p-type AlInAs electric field reduction layer is grown on the i-type AlInAs avalanche multiplication layer. Transition layers are grown to cover the top surface of the electric field reduction layer. After the covering of the top surface of the electric field reduction layer by the transition layers, the temperature of the growth process is increased and an n?-type InGaAs light absorption layer is grown on the transition layer at a temperature higher than the growth temperature of the electric field reduction layer. The growth temperature of the transition layers is lower than that of the n?-type InGaAs light absorption layer. The transition layers have higher resistance to surface defects than the electric field reduction layer at temperatures higher than the growth temperature of the electric field reduction layer.Type: ApplicationFiled: July 18, 2013Publication date: May 15, 2014Inventors: Harunaka Yamaguchi, Ryota Takemura
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Publication number: 20130070798Abstract: A semiconductor laser includes a semiconductor laser portion including an active layer portion having a p-type cladding layer, an active layer, and an n-type cladding layer on a p-type InP semiconductor substrate; and current confining structures that fill spaces on both sides of the semiconductor laser portion. Each of the current confining structures includes a first p-type InP layer, a Ru-doped InP layer, and a second p-type InP layer. The Ru-doped InP layer is in contact only with the first and second p-type InP layers. To obtain the structure, timing of introduction of a halogen-containing gas is adjusted.Type: ApplicationFiled: August 16, 2012Publication date: March 21, 2013Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Go Sakaino, Harunaka Yamaguchi, Takashi Nagira
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Publication number: 20100316080Abstract: A semiconductor optical element includes a p-type InP substrate doped with Zn; and a diffusion blocking layer doped with Ru, a p-type InP cladding layer, an active layer, and an n-type InP cladding layer sequentially arranged on the p-type InP substrate.Type: ApplicationFiled: February 5, 2010Publication date: December 16, 2010Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Harunaka Yamaguchi, Chikara Watatani, Masayoshi Takemi