Patents by Inventor Harunobu Kondo

Harunobu Kondo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICE HAVING L-SHAPED CONDUCTIVE PATTERN
    Publication number: 20230326852
    Abstract: Disclosed herein is an apparatus that includes a semiconductor substrate having a main surface extending in a first direction and a second direction different from the first direction and a conductive pattern formed over the main surface of the semiconductor substrate. The conductive pattern includes a first section extending in the first direction, a second section extending in the second direction, and a third section connected between the first and second sections. The third section of the conductive pattern has a first slit extending in a third direction different from the first and second directions.
    Type: Application
    Filed: April 6, 2022
    Publication date: October 12, 2023
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Harunobu Kondo, Kazuteru Ishizuka, Wataru Nobehara, Ryosuke Yatsushiro, Makoto Saito
  • Semiconductor device having L-shaped conductive pattern
    Patent number: 11764152
    Abstract: Disclosed herein is an apparatus that includes a semiconductor substrate having a main surface extending in a first direction and a second direction different from the first direction and a conductive pattern formed over the main surface of the semiconductor substrate. The conductive pattern includes a first section extending in the first direction, a second section extending in the second direction, and a third section connected between the first and second sections. The third section of the conductive pattern has a first slit extending in a third direction different from the first and second directions.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: September 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Harunobu Kondo, Kazuteru Ishizuka, Wataru Nobehara, Ryosuke Yatsushiro, Makoto Saito
  • Apparatuses and methods for semiconductor circuit layout
    Patent number: 10431647
    Abstract: Apparatuses including compensation capacitors are described. An example apparatus includes: first, second and third capacitors arranged such that the second capacitor is sandwiched between the first and third capacitors, each of the first, second and third capacitors including first and second electrodes. The first electrodes of the first, second and third capacitors are electrically coupled in common to one another. The second electrodes of the first and third capacitors are electrically coupled in common to each other. The second electrode of the second capacitor is electrically insulated from the second electrodes of the first and third capacitors.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Harunobu Kondo, Kenichi Echigoya
  • APPARATUSES AND METHODS FOR SEMICONDUCTOR CIRCUIT LAYOUT
    Publication number: 20180247998
    Abstract: Apparatuses including compensation capacitors are described. An example apparatus includes: first, second and third capacitors arranged such that the second capacitor is sandwiched between the first and third capacitors, each of the first, second and third capacitors including first and second electrodes. The first electrodes of the first, second and third capacitors are electrically coupled in common to one another. The second electrodes of the first and third capacitors are electrically coupled in common to each other. The second electrode of the second capacitor is electrically insulated from the second electrodes of the first and third capacitors.
    Type: Application
    Filed: April 30, 2018
    Publication date: August 30, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Harunobu Kondo, Kenichi Echigoya
  • Apparatuses and methods for semiconductor circuit layout
    Patent number: 9991331
    Abstract: Apparatuses including compensation capacitors are described. An example apparatus includes: first, second and third capacitors arranged such that the second capacitor is sandwiched between the first and third capacitors, each of the first, second and third capacitors including first and second electrodes. The first electrodes of the first, second and third capacitors are electrically coupled in common to one another. The second electrodes of the first and third capacitors are electrically coupled in common to each other. The second electrode of the second capacitor is electrically insulated from the second electrodes of the first and third capacitors.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: June 5, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Harunobu Kondo, Kenichi Echigoya
  • APPARATUSES AND METHODS FOR SEMICONDUCTOR CIRCUIT LAYOUT
    Publication number: 20180090557
    Abstract: Apparatuses including compensation capacitors are described. An example apparatus includes: first, second and third capacitors arranged such that the second capacitor is sandwiched between the first and third capacitors, each of the first, second and third capacitors including first and second electrodes. The first electrodes of the first, second and third capacitors are electrically coupled in common to one another. The second electrodes of the first and third capacitors are electrically coupled in common to each other. The second electrode of the second capacitor is electrically insulated from the second electrodes of the first and third capacitors.
    Type: Application
    Filed: September 26, 2016
    Publication date: March 29, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Harunobu Kondo, Kenichi Echigoya