Abstract: A semiconductor storing device and a redundancy method thereof are provided. The semiconductor storing device is for example a NAND flash memory, which includes: a storing array including a storing area and a redundancy storing area with a redundancy element; a page buffer; a row selecting circuit; an ECC circuit; and an I/O buffer. The row selecting circuit transforms defect data included in core data retained by a cache register into redundancy data retained by a redundancy cache register, and provides the transformed data to the ECC circuit, and the data corrected by the ECC circuit as the core data is written to the cache register again. During this period, the row selecting circuit outputs the corrected data retained in the cache register to the I/O buffer.

Abstract: A semiconductor storing device and a redundancy method thereof are provided. The semiconductor storing device is for example a NAND flash memory, which includes: a storing array including a storing area and a redundancy storing area with a redundancy element; a page buffer; a row selecting circuit; an ECC circuit; and an I/O buffer. The row selecting circuit transforms defect data included in core data retained by a cache register into redundancy data retained by a redundancy cache register, and provides the transformed data to the ECC circuit, and the data corrected by the ECC circuit as the core data is written to the cache register again. During this period, the row selecting circuit outputs the corrected data retained in the cache register to the I/O buffer.

Abstract: A semiconductor device includes: a latch circuit that latches a given signal in a test mode; and a generating circuit that generates a signal that defines a program voltage used for programming of a memory cell in accordance with the signal latched in the latch circuit. The generating circuit includes: a circuit that generates the signal that defines an initial voltage of the program voltage; a circuit that generates the signal that defines a pulse width of the program voltage; and a circuit that generates the signal that defines a step width of the program voltage when the program voltage is a voltage that increases stepwise.

Abstract: A semiconductor device includes: a latch circuit that latches a given signal in a test mode; and a generating circuit that generates a signal that defines a program voltage used for programming of a memory cell in accordance with the signal latched in the latch circuit. The generating circuit includes: a circuit that generates the signal that defines an initial voltage of the program voltage; a circuit that generates the signal that defines a pulse width of the program voltage; and a circuit that generates the signal that defines a step width of the program voltage when the program voltage is a voltage that increases stepwise.

Abstract: A semiconductor memory device includes a plurality of input/output terminals, a memory cell array which are divided into blocks respectively corresponding to the input/output terminals such that only one of the blocks corresponds to a given one of the input/output terminals, sense amplifiers, which are connected to the blocks at a side thereof, and amplify data of the memory cell array, switches which are respectively connected to the sense amplifiers, and signal lines, which connect the sense amplifiers to a corresponding one of the input/output terminals via the switches.

Abstract: A plurality of memory blocks including a plurality of memory regions as minimum erase units is formed. When an erase control signal supplied in response to an erase command indicates a first erase mode, an erase selecting circuit selects all of the memory regions in the memory block selected by a first address signal. An erase control circuit erases data of the memory regions selected by the erase selecting circuit. Namely, erasure of the data is carried out by the memory block when the erase control signal indicates the first erase mode. Since the memory regions from which the data are erased can be selected simultaneously by one erase command, it is possible to reduce the number of input of erase commands. Therefore, it is possible to simplify a system program to be carried out by a CPU or the like which controls a semiconductor memory.

Abstract: A semiconductor memory device includes a plurality of input/output terminals, a memory cell array which are divided into blocks respectively corresponding to the input/output terminals such that only one of the blocks corresponds to a given one of the input/output terminals, sense amplifiers, which are connected to the blocks at a side thereof, and amplify data of the memory cell array, switches which are respectively connected to the sense amplifiers, and signal lines, which connect the sense amplifiers to a corresponding one of the input/output terminals via the switches.